Searched refs:banks (Results 1 - 25 of 77) sorted by relevance

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/linux-master/arch/x86/kernel/cpu/mce/
H A Dthreshold.c46 storm->banks[bank].history = ~0ull;
47 storm->banks[bank].timestamp = jiffies;
74 storm->banks[bank].in_storm_mode = true;
89 storm->banks[bank].history = 0;
90 storm->banks[bank].in_storm_mode = false;
92 /* If no banks left in storm mode, stop polling. */
104 /* No tracking needed for banks that do not support CMCI */
105 if (storm->banks[mce->bank].poll_only)
116 if (!storm->banks[mce->bank].in_storm_mode) {
117 delta = now - storm->banks[mc
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H A Dintel.c27 * Also supports reliable discovery of shared banks.
36 * some MCA banks are shared across cpus. When a cpu is offlined, cmci_clear()
37 * disables CMCI on all banks owned by the cpu and clears this bitfield. At
39 * taking ownership of some of the shared MCA banks that were previously
78 static int cmci_supported(int *banks) argument
97 *banks = min_t(unsigned, MAX_NR_BANKS, cap & 0xff);
182 /* Skip banks in firmware first mode */
240 storm->banks[bank].poll_only = true;
256 * We are able to set thresholds for some banks that
271 * Enable CMCI (Corrected Machine Check Interrupt) for available MCE banks
276 cmci_discover(int banks) argument
309 int banks; local
343 int banks; local
355 int banks; local
365 int banks; local
378 int banks; local
385 int banks; local
406 int banks; local
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/linux-master/arch/arm/mach-omap2/
H A Dpowerdomains54xx_data.c36 .banks = 5,
62 .banks = 2,
91 .banks = 1,
109 .banks = 1,
126 .banks = 1,
142 .banks = 1,
159 .banks = 2,
188 .banks = 3,
209 .banks = 1,
227 .banks
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H A Dpowerdomains7xx_data.c37 .banks = 4,
78 .banks = 2,
92 .banks = 1,
105 .banks = 2,
119 .banks = 1,
132 .banks = 1,
144 .banks = 5,
170 .banks = 1,
186 .banks = 1,
201 .banks
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H A Dpowerdomains2xxx_data.c31 .banks = 1,
46 .banks = 1,
61 .banks = 3,
87 .banks = 1,
H A Dpowerdomains2xxx_3xxx_data.c47 .banks = 1,
H A Dpowerdomains44xx_data.c38 .banks = 5,
63 .banks = 1,
81 .banks = 2,
101 .banks = 1,
119 .banks = 3,
140 .banks = 1,
157 .banks = 1,
174 .banks = 1,
190 .banks = 1,
207 .banks
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H A Dpowerdomains43xx_data.c23 .banks = 1,
37 .banks = 3,
65 .banks = 1,
95 .banks = 4,
H A Dpowerdomains3xxx_data.c37 .banks = 4,
59 .banks = 1,
75 .banks = 1,
100 .banks = 2,
122 .banks = 2,
139 .banks = 2,
156 .banks = 1,
171 .banks = 1,
192 .banks = 1,
207 .banks
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H A Dpowerdomains33xx_data.c25 .banks = 1,
76 .banks = 3,
119 .banks = 3,
/linux-master/drivers/net/ethernet/intel/ice/
H A Dice_nvm.c249 struct ice_bank_info *banks = &hw->flash.banks; local
256 offset = banks->nvm_ptr;
257 size = banks->nvm_size;
258 active_bank = banks->nvm_bank;
261 offset = banks->orom_ptr;
262 size = banks->orom_size;
263 active_bank = banks->orom_bank;
266 offset = banks->netlist_ptr;
267 size = banks
942 struct ice_bank_info *banks = &hw->flash.banks; local
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/linux-master/drivers/memory/
H A Dfsl_ifc.c42 * This function walks IFC banks comparing "Base address" field of the CSPR
54 for (i = 0; i < fsl_ifc_ctrl_dev->banks; i++) {
199 * resources for the NAND banks themselves are allocated
205 int version, banks; local
235 banks = (version == FSL_IFC_VERSION_1_0_0) ? 4 : 8;
236 dev_info(&dev->dev, "IFC version %d.%d, %d banks\n",
237 version >> 24, (version >> 16) & 0xf, banks);
240 fsl_ifc_ctrl_dev->banks = banks;
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_aca.c49 static void aca_banks_init(struct aca_banks *banks) argument
51 if (!banks)
54 memset(banks, 0, sizeof(*banks));
55 INIT_LIST_HEAD(&banks->list);
58 static int aca_banks_add_bank(struct aca_banks *banks, struct aca_bank *bank) argument
72 list_add_tail(&node->node, &banks->list);
74 banks->nr_banks++;
79 static void aca_banks_release(struct aca_banks *banks) argument
83 list_for_each_entry_safe(node, tmp, &banks
130 aca_smu_get_valid_aca_banks(struct amdgpu_device *adev, enum aca_error_type type, int start, int count, struct aca_banks *banks) argument
356 aca_dispatch_banks(struct aca_handle_manager *mgr, struct aca_banks *banks, enum aca_error_type type, bank_handler_t handler, void *data) argument
385 struct aca_banks banks; local
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/linux-master/drivers/clk/tegra/
H A Dclk.c213 static int tegra_clk_periph_ctx_init(int banks) argument
215 periph_state_ctx = kcalloc(2 * banks, sizeof(*periph_state_ctx),
223 struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks) argument
227 if (WARN_ON(banks > ARRAY_SIZE(periph_regs)))
230 periph_clk_enb_refcnt = kcalloc(32 * banks,
236 periph_banks = banks;
247 if (tegra_clk_periph_ctx_init(banks)) {
/linux-master/drivers/pinctrl/qcom/
H A Dpinctrl-ssbi-gpio.c325 u8 banks = 0; local
335 banks |= BIT(2);
337 banks |= BIT(3);
341 banks |= BIT(2);
343 banks |= BIT(3);
354 banks |= BIT(2);
356 banks |= BIT(3);
360 banks |= BIT(3);
364 banks |= BIT(0) | BIT(1);
369 banks |
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/linux-master/drivers/crypto/intel/qat/qat_common/
H A Dadf_vf_isr.c166 struct adf_etr_bank_data *bank = &etr_data->banks[0];
205 tasklet_init(&priv_data->banks[0].resp_handler, adf_response_handler,
206 (unsigned long)priv_data->banks);
214 tasklet_disable(&priv_data->banks[0].resp_handler);
215 tasklet_kill(&priv_data->banks[0].resp_handler);
H A Dadf_hw_arbiter.c21 void __iomem *csr = accel_dev->transport->banks[0].csr_addr;
89 csr = accel_dev->transport->banks[0].csr_addr;
109 void __iomem *csr = accel_dev->transport->banks[0].csr_addr;
H A Dadf_isr.c191 free_irq(irq, &etr_data->banks[i]);
212 /* Request msix irq for all banks unless SR-IOV enabled */
215 struct adf_etr_bank_data *bank = &etr_data->banks[i];
303 tasklet_init(&priv_data->banks[i].resp_handler,
305 (unsigned long)&priv_data->banks[i]);
316 tasklet_disable(&priv_data->banks[i].resp_handler);
317 tasklet_kill(&priv_data->banks[i].resp_handler);
H A Dadf_transport_internal.h46 struct adf_etr_bank_data *banks; member in struct:adf_etr_data
H A Dadf_gen2_config.c16 int banks = GET_MAX_BANKS(accel_dev); local
24 instances = min(cpus, banks);
115 int banks = GET_MAX_BANKS(accel_dev); local
123 instances = min(cpus, banks);
H A Dadf_gen4_config.c17 int banks = GET_MAX_BANKS(accel_dev); local
25 instances = min(cpus, banks / 2);
123 int banks = GET_MAX_BANKS(accel_dev); local
131 instances = min(cpus, banks);
/linux-master/arch/x86/boot/
H A Dvesa.h44 u8 banks; /* 26 */ member in struct:vesa_mode_info
/linux-master/drivers/pinctrl/vt8500/
H A Dpinctrl-wmt.h57 const struct wmt_pinctrl_bank_registers *banks; member in struct:wmt_pinctrl_data
/linux-master/arch/mips/bcm63xx/
H A Dcpu.c258 unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0; local
274 banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
282 banks = 2;
291 return 1 << (cols + rows + (is_32bits + 1) + banks);
/linux-master/drivers/soc/mediatek/
H A Dmtk-svs.c377 * @banks: svs banks that svs platform supports
385 * @bank_max: total number of svs banks
391 struct svs_bank *banks; member in struct:svs_platform
404 struct svs_bank *banks; member in struct:svs_platform_data
734 svsb = &svsp->banks[idx];
896 svsb = &svsp->banks[idx];
1215 struct svs_bank *svsb = &svsp->banks[bank_idx];
1283 struct svs_bank *svsb = &svsp->banks[bank_idx];
1293 struct svs_bank *svsb = &svsp->banks[bank_id
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