Searched refs:bank_width (Results 1 - 11 of 11) sorted by relevance

/linux-master/arch/arm/mach-omap1/
H A Dgpio15xx.c46 .bank_width = 16,
87 .bank_width = 16,
H A Dgpio16xx.c53 .bank_width = 16,
98 .bank_width = 16,
126 .bank_width = 16,
154 .bank_width = 16,
182 .bank_width = 16,
/linux-master/drivers/gpio/
H A Dgpio-brcmstb.c597 u32 bank_width; local
642 bank_width) {
647 * If bank_width is 0, then there is an empty bank in the
650 if (bank_width == 0) {
666 if (bank_width <= 0 || bank_width > MAX_GPIO_PER_BANK) {
667 dev_err(dev, "Invalid bank width %d\n", bank_width);
671 bank->width = bank_width;
H A Dgpio-omap.c1360 .bank_width = 32,
1366 .bank_width = 32,
1372 .bank_width = 32,
1421 bank->width = pdata->bank_width;
/linux-master/include/linux/platform_data/
H A Dgpio-omap.h182 int bank_width; /* GPIO bank width */ member in struct:omap_gpio_platform_data
/linux-master/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_debug.c133 "plane_state->tiling_info.gfx8.bank_width = %d;\n"
144 plane_state->tiling_info.gfx8.bank_width,
225 "plane_info->tiling_info.gfx8.bank_width = %d;\n"
236 update->plane_info->tiling_info.gfx8.bank_width,
/linux-master/drivers/edac/
H A Dthunderx_edac.c196 int bank_width; member in struct:thunderx_lmc
505 bank ^= get_bits(addr, 12 + lmc->xbits, lmc->bank_width);
746 lmc->bank_width = (FIELD_GET(LMC_DDR_PLL_CTL_DDR4, lmc_ddr_pll_ctl) &&
756 lmc->col_hi_lsb = lmc->bank_lsb + lmc->bank_width;
/linux-master/drivers/gpu/drm/amd/display/dc/
H A Ddc_hw_types.h337 unsigned int bank_width; member in struct:dc_tiling_info::__anon218
/linux-master/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_mem_input.c452 GRPH_BANK_WIDTH, info->gfx8.bank_width,
469 GRPH_BANK_WIDTH, info->gfx8.bank_width,
/linux-master/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_mem_input_v.c175 set_reg_field_value(value, info->gfx8.bank_width,
/linux-master/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_plane.c198 tiling_info->gfx8.bank_width = bankw;

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