Searched refs:_shift (Results 1 - 25 of 225) sorted by relevance

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/linux-master/drivers/clk/sprd/
H A Dmux.h32 #define _SPRD_MUX_CLK(_shift, _width, _table) \
34 .shift = _shift, \
40 _reg, _shift, _width, _flags, _fn) \
42 .mux = _SPRD_MUX_CLK(_shift, _width, _table), \
52 _reg, _shift, _width, _flags) \
54 _reg, _shift, _width, _flags, \
58 _shift, _width, _flags) \
60 _reg, _shift, _width, _flags)
63 _reg, _shift, _width, _flags) \
65 _reg, _shift, _widt
[all...]
H A Ddiv.h28 #define _SPRD_DIV_CLK(_offset, _shift, _width) \
31 .shift = _shift, \
41 _shift, _width, _flags, _fn) \
43 .div = _SPRD_DIV_CLK(_offset, _shift, _width), \
53 _shift, _width, _flags) \
55 _shift, _width, _flags, CLK_HW_INIT)
58 _shift, _width, _flags) \
60 _shift, _width, _flags, CLK_HW_INIT_FW_NAME)
63 _shift, _width, _flags) \
65 _shift, _widt
[all...]
/linux-master/drivers/clk/sunxi-ng/
H A Dccu_mult.h17 #define _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, _offset, _min, _max) \
22 .shift = _shift, \
26 #define _SUNXI_CCU_MULT_MIN(_shift, _width, _min) \
27 _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, 1, _min, 0)
29 #define _SUNXI_CCU_MULT_OFFSET(_shift, _width, _offset) \
30 _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, _offset, 1, 0)
32 #define _SUNXI_CCU_MULT(_shift, _width) \
33 _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, 1, 1, 0)
H A Dccu_mux.h32 #define _SUNXI_CCU_MUX_TABLE(_shift, _width, _table) \
34 .shift = _shift, \
39 #define _SUNXI_CCU_MUX(_shift, _width) \
40 _SUNXI_CCU_MUX_TABLE(_shift, _width, NULL)
50 _reg, _shift, _width, _gate, \
54 .mux = _SUNXI_CCU_MUX_TABLE(_shift, _width, _table), \
66 _table, _reg, _shift, \
69 _table, _reg, _shift, \
74 _reg, _shift, _width, _gate, \
77 _table, _reg, _shift, \
[all...]
H A Dccu_div.h43 #define _SUNXI_CCU_DIV_TABLE_FLAGS(_shift, _width, _table, _flags) \
45 .shift = _shift, \
51 #define _SUNXI_CCU_DIV_TABLE(_shift, _width, _table) \
52 _SUNXI_CCU_DIV_TABLE_FLAGS(_shift, _width, _table, 0)
54 #define _SUNXI_CCU_DIV_OFFSET_MAX_FLAGS(_shift, _width, _off, _max, _flags) \
56 .shift = _shift, \
63 #define _SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, _max, _flags) \
64 _SUNXI_CCU_DIV_OFFSET_MAX_FLAGS(_shift, _width, 1, _max, _flags)
66 #define _SUNXI_CCU_DIV_FLAGS(_shift, _width, _flags) \
67 _SUNXI_CCU_DIV_MAX_FLAGS(_shift, _widt
[all...]
H A Dccu_phase.h20 #define SUNXI_CCU_PHASE(_struct, _name, _parent, _reg, _shift, _width, _flags) \
22 .shift = _shift, \
/linux-master/drivers/clk/actions/
H A Dowl-mux.h27 #define OWL_MUX_HW(_reg, _shift, _width) \
30 .shift = _shift, \
35 _shift, _width, _flags) \
37 .mux_hw = OWL_MUX_HW(_reg, _shift, _width), \
H A Dowl-pll.h41 #define OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
47 .shift = _shift, \
56 _shift, _width, _min_mul, _max_mul, _table, _flags) \
58 .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
71 _shift, _width, _min_mul, _max_mul, _table, _flags) \
73 .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
85 _shift, _width, _min_mul, _max_mul, _delay, _table, \
88 .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
H A Dowl-factor.h35 #define OWL_FACTOR_HW(_reg, _shift, _width, _fct_flags, _table) \
38 .shift = _shift, \
45 _shift, _width, _table, _fct_flags, _flags) \
47 .factor_hw = OWL_FACTOR_HW(_reg, _shift, \
H A Dowl-divider.h29 #define OWL_DIVIDER_HW(_reg, _shift, _width, _div_flags, _table) \
32 .shift = _shift, \
39 _shift, _width, _table, _div_flags, _flags) \
41 .div_hw = OWL_DIVIDER_HW(_reg, _shift, _width, \
/linux-master/drivers/pinctrl/mediatek/
H A Dpinctrl-mtmips.h12 #define GRP(_name, _func, _mask, _shift) \
13 { .name = _name, .mask = _mask, .shift = _shift, \
17 #define GRP_G(_name, _func, _mask, _gpio, _shift) \
18 { .name = _name, .mask = _mask, .shift = _shift, \
/linux-master/drivers/clk/mediatek/
H A Dclk-mux.h43 _mux_clr_ofs, _shift, _width, _gate, _upd_ofs, \
51 .mux_shift = _shift, \
63 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
67 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
71 _mux_ofs, _mux_set_ofs, _mux_clr_ofs, _shift, \
75 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
82 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
85 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
91 _shift, _width, _gate, _upd_ofs, _upd, _flags) \
94 _shift, _widt
[all...]
H A Dclk-mt8186-vdec.c39 #define GATE_VDEC0(_id, _name, _parent, _shift) \
40 GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
42 #define GATE_VDEC1(_id, _name, _parent, _shift) \
43 GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
45 #define GATE_VDEC2(_id, _name, _parent, _shift) \
46 GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
48 #define GATE_VDEC3(_id, _name, _parent, _shift) \
49 GATE_MTK(_id, _name, _parent, &vdec3_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
H A Dclk-mt8183-ipu_conn.c44 #define GATE_IPU_CONN(_id, _name, _parent, _shift) \
45 GATE_MTK(_id, _name, _parent, &ipu_conn_cg_regs, _shift, \
48 #define GATE_IPU_CONN_APB(_id, _name, _parent, _shift) \
49 GATE_MTK(_id, _name, _parent, &ipu_conn_apb_cg_regs, _shift, \
52 #define GATE_IPU_CONN_AXI_I(_id, _name, _parent, _shift) \
53 GATE_MTK(_id, _name, _parent, &ipu_conn_axi_cg_regs, _shift, \
56 #define GATE_IPU_CONN_AXI1_I(_id, _name, _parent, _shift) \
57 GATE_MTK(_id, _name, _parent, &ipu_conn_axi1_cg_regs, _shift, \
60 #define GATE_IPU_CONN_AXI2_I(_id, _name, _parent, _shift) \
61 GATE_MTK(_id, _name, _parent, &ipu_conn_axi2_cg_regs, _shift, \
[all...]
H A Dclk-mt8195-infra_ao.c44 #define GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, _flag) \
45 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \
48 #define GATE_INFRA_AO0(_id, _name, _parent, _shift) \
49 GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0)
51 #define GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, _flag) \
52 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao1_cg_regs, _shift, \
55 #define GATE_INFRA_AO1(_id, _name, _parent, _shift) \
56 GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0)
58 #define GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, _flag) \
59 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao2_cg_regs, _shift, \
[all...]
H A Dclk-mt8188-infra_ao.c45 #define GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, _flag) \
46 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \
49 #define GATE_INFRA_AO0(_id, _name, _parent, _shift) \
50 GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0)
52 #define GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, _flag) \
53 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao1_cg_regs, _shift, \
56 #define GATE_INFRA_AO1(_id, _name, _parent, _shift) \
57 GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0)
59 #define GATE_INFRA_AO2(_id, _name, _parent, _shift) \
60 GATE_MTK(_id, _name, _parent, &infra_ao2_cg_regs, _shift,
[all...]
H A Dclk-mt8195-vdo1.c43 #define GATE_VDO1_0(_id, _name, _parent, _shift) \
44 GATE_MTK(_id, _name, _parent, &vdo1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
46 #define GATE_VDO1_1(_id, _name, _parent, _shift) \
47 GATE_MTK(_id, _name, _parent, &vdo1_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
49 #define GATE_VDO1_2(_id, _name, _parent, _shift) \
50 GATE_MTK(_id, _name, _parent, &vdo1_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
52 #define GATE_VDO1_2_FLAGS(_id, _name, _parent, _shift, _flags) \
53 GATE_MTK_FLAGS(_id, _name, _parent, &vdo1_2_cg_regs, _shift, \
56 #define GATE_VDO1_3(_id, _name, _parent, _shift) \
57 GATE_MTK(_id, _name, _parent, &vdo1_3_cg_regs, _shift,
[all...]
H A Dclk-mt8188-vdo1.c46 #define GATE_VDO1_0(_id, _name, _parent, _shift) \
47 GATE_MTK(_id, _name, _parent, &vdo1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
49 #define GATE_VDO1_1(_id, _name, _parent, _shift) \
50 GATE_MTK(_id, _name, _parent, &vdo1_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
52 #define GATE_VDO1_2(_id, _name, _parent, _shift) \
53 GATE_MTK(_id, _name, _parent, &vdo1_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
55 #define GATE_VDO1_3(_id, _name, _parent, _shift) \
56 GATE_MTK(_id, _name, _parent, &vdo1_3_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
58 #define GATE_VDO1_3_FLAGS(_id, _name, _parent, _shift, _flags) \
59 GATE_MTK_FLAGS(_id, _name, _parent, &vdo1_3_cg_regs, _shift, \
[all...]
H A Dclk-mt8195-vdec.c31 #define GATE_VDEC0(_id, _name, _parent, _shift) \
32 GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
34 #define GATE_VDEC1(_id, _name, _parent, _shift) \
35 GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
37 #define GATE_VDEC2(_id, _name, _parent, _shift) \
38 GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
H A Dclk-mt8188-vdec.c32 #define GATE_VDEC0(_id, _name, _parent, _shift) \
33 GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
35 #define GATE_VDEC1(_id, _name, _parent, _shift) \
36 GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
38 #define GATE_VDEC2(_id, _name, _parent, _shift) \
39 GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
H A Dclk-mt7986-eth.c23 #define GATE_SGMII0(_id, _name, _parent, _shift) \
24 GATE_MTK(_id, _name, _parent, &sgmii0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
39 #define GATE_SGMII1(_id, _name, _parent, _shift) \
40 GATE_MTK(_id, _name, _parent, &sgmii1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
55 #define GATE_ETH(_id, _name, _parent, _shift) \
56 GATE_MTK(_id, _name, _parent, &eth_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
H A Dclk-mt8192-vdec.c33 #define GATE_VDEC0(_id, _name, _parent, _shift) \
34 GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
36 #define GATE_VDEC1(_id, _name, _parent, _shift) \
37 GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
39 #define GATE_VDEC2(_id, _name, _parent, _shift) \
40 GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
H A Dclk-mt8195-vdo0.c31 #define GATE_VDO0_0(_id, _name, _parent, _shift) \
32 GATE_MTK(_id, _name, _parent, &vdo0_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
34 #define GATE_VDO0_1(_id, _name, _parent, _shift) \
35 GATE_MTK(_id, _name, _parent, &vdo0_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
37 #define GATE_VDO0_2(_id, _name, _parent, _shift) \
38 GATE_MTK(_id, _name, _parent, &vdo0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
40 #define GATE_VDO0_2_FLAGS(_id, _name, _parent, _shift, _flags) \
41 GATE_MTK_FLAGS(_id, _name, _parent, &vdo0_2_cg_regs, _shift, \
H A Dclk-mt8188-vdo0.c34 #define GATE_VDO0_0(_id, _name, _parent, _shift) \
35 GATE_MTK(_id, _name, _parent, &vdo0_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
37 #define GATE_VDO0_1(_id, _name, _parent, _shift) \
38 GATE_MTK(_id, _name, _parent, &vdo0_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
40 #define GATE_VDO0_2(_id, _name, _parent, _shift) \
41 GATE_MTK(_id, _name, _parent, &vdo0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
43 #define GATE_VDO0_2_FLAGS(_id, _name, _parent, _shift, _flags) \
44 GATE_MTK_FLAGS(_id, _name, _parent, &vdo0_2_cg_regs, _shift, \
/linux-master/drivers/iio/dac/
H A Dad5686.c191 #define AD5868_CHANNEL(chan, addr, bits, _shift) { \
203 .shift = (_shift), \
208 #define DECLARE_AD5693_CHANNELS(name, bits, _shift) \
210 AD5868_CHANNEL(0, 0, bits, _shift), \
213 #define DECLARE_AD5338_CHANNELS(name, bits, _shift) \
215 AD5868_CHANNEL(0, 1, bits, _shift), \
216 AD5868_CHANNEL(1, 8, bits, _shift), \
219 #define DECLARE_AD5686_CHANNELS(name, bits, _shift) \
221 AD5868_CHANNEL(0, 1, bits, _shift), \
222 AD5868_CHANNEL(1, 2, bits, _shift), \
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