Searched refs:_parent (Results 1 - 25 of 204) sorted by relevance

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/linux-master/drivers/clk/actions/
H A Dowl-fixed-factor.h16 #define OWL_FIX_FACT(_struct, _name, _parent, _mul, _div, _flags) \
21 _parent, \
H A Dowl-composite.h37 #define OWL_COMP_DIV(_struct, _name, _parent, \
46 _parent, \
52 #define OWL_COMP_DIV_FIXED(_struct, _name, _parent, \
60 _parent, \
66 #define OWL_COMP_FACTOR(_struct, _name, _parent, \
75 _parent, \
81 #define OWL_COMP_FIXED_FACTOR(_struct, _name, _parent, \
91 _parent, \
97 #define OWL_COMP_PASS(_struct, _name, _parent, \
105 _parent, \
[all...]
/linux-master/drivers/clk/sprd/
H A Dgate.h31 #define SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
42 .hw.init = _fn(_name, _parent, \
47 #define SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg, \
50 SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
54 #define SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, _sc_offset, \
56 SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg, \
60 #define SPRD_SC_GATE_CLK(_struct, _name, _parent, _reg, _sc_offset, \
62 SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, _sc_offset, \
66 #define SPRD_GATE_CLK(_struct, _name, _parent, _reg, \
68 SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _re
[all...]
H A Dcomposite.h21 #define SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \
30 .hw.init = _fn(_name, _parent, \
35 #define SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, _table, \
37 SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \
41 #define SPRD_COMP_CLK(_struct, _name, _parent, _reg, _mshift, \
43 SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, NULL, \
46 #define SPRD_COMP_CLK_DATA_TABLE(_struct, _name, _parent, _reg, _table, \
49 SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \
54 #define SPRD_COMP_CLK_DATA(_struct, _name, _parent, _reg, _mshift, \
56 SPRD_COMP_CLK_DATA_TABLE(_struct, _name, _parent, _re
[all...]
H A Dpll.h64 #define SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, \
80 .hw.init = _fn(_name, _parent, \
85 #define SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \
88 SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, _regs_num, \
92 #define SPRD_PLL_WITH_ITABLE_K(_struct, _name, _parent, _reg, \
95 SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \
99 #define SPRD_PLL_WITH_ITABLE_1K(_struct, _name, _parent, _reg, \
101 SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \
105 #define SPRD_PLL_FW_NAME(_struct, _name, _parent, _reg, _regs_num, \
108 SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _re
[all...]
H A Ddiv.h40 #define SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _offset, \
47 .hw.init = _fn(_name, _parent, \
52 #define SPRD_DIV_CLK(_struct, _name, _parent, _reg, \
54 SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, 0x0, \
57 #define SPRD_DIV_CLK_FW_NAME(_struct, _name, _parent, _reg, \
59 SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, 0x0, \
62 #define SPRD_DIV_CLK_HW(_struct, _name, _parent, _reg, \
64 SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, 0x0, \
/linux-master/drivers/clk/sunxi-ng/
H A Dccu_gate.h19 #define SUNXI_CCU_GATE(_struct, _name, _parent, _reg, _gate, _flags) \
25 _parent, \
31 #define SUNXI_CCU_GATE_HW(_struct, _name, _parent, _reg, _gate, _flags) \
37 _parent, \
43 #define SUNXI_CCU_GATE_FW(_struct, _name, _parent, _reg, _gate, _flags) \
49 _parent, \
59 #define SUNXI_CCU_GATE_HWS(_struct, _name, _parent, _reg, _gate, _flags) \
65 _parent, \
71 #define SUNXI_CCU_GATE_HWS_WITH_PREDIV(_struct, _name, _parent, _reg, \
80 _parent, \
[all...]
H A Dccu_phase.h20 #define SUNXI_CCU_PHASE(_struct, _name, _parent, _reg, _shift, _width, _flags) \
27 _parent, \
/linux-master/drivers/clk/renesas/
H A Drcar-gen4-cpg.h36 #define DEF_GEN4_SDH(_name, _id, _parent, _offset) \
37 DEF_BASE(_name, _id, CLK_TYPE_GEN4_SDH, _parent, .offset = _offset)
39 #define DEF_GEN4_SD(_name, _id, _parent, _offset) \
40 DEF_BASE(_name, _id, CLK_TYPE_GEN4_SD, _parent, .offset = _offset)
47 #define DEF_GEN4_OSC(_name, _id, _parent, _div) \
48 DEF_BASE(_name, _id, CLK_TYPE_GEN4_OSC, _parent, .div = _div)
50 #define DEF_GEN4_Z(_name, _id, _type, _parent, _div, _offset) \
51 DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
H A Drenesas-cpg-mssr.h46 #define DEF_BASE(_name, _id, _type, _parent...) \
47 DEF_TYPE(_name, _id, _type, .parent = _parent)
51 #define DEF_FIXED(_name, _id, _parent, _div, _mult) \
52 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
53 #define DEF_DIV6P1(_name, _id, _parent, _offset) \
54 DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
55 #define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \
56 DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
75 #define DEF_MOD(_name, _mod, _parent...) \
76 { .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }
[all...]
H A Drzg2l-cpg.h131 #define DEF_BASE(_name, _id, _type, _parent...) \
132 DEF_TYPE(_name, _id, _type, .parent = _parent)
133 #define DEF_SAMPLL(_name, _id, _parent, _conf) \
134 DEF_TYPE(_name, _id, CLK_TYPE_SAM_PLL, .parent = _parent, .conf = _conf)
135 #define DEF_G3S_PLL(_name, _id, _parent, _conf) \
136 DEF_TYPE(_name, _id, CLK_TYPE_G3S_PLL, .parent = _parent, .conf = _conf)
139 #define DEF_FIXED(_name, _id, _parent, _mult, _div) \
140 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
141 #define DEF_DIV(_name, _id, _parent, _conf, _dtable) \
143 .parent = _parent,
[all...]
H A Drcar-gen3-cpg.h37 #define DEF_GEN3_SDH(_name, _id, _parent, _offset) \
38 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SDH, _parent, .offset = _offset)
40 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \
41 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
53 #define DEF_GEN3_OSC(_name, _id, _parent, _div) \
54 DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div)
60 #define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \
61 DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
/linux-master/drivers/clk/mediatek/
H A Dclk-mt8186-vdec.c39 #define GATE_VDEC0(_id, _name, _parent, _shift) \
40 GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
42 #define GATE_VDEC1(_id, _name, _parent, _shift) \
43 GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
45 #define GATE_VDEC2(_id, _name, _parent, _shift) \
46 GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
48 #define GATE_VDEC3(_id, _name, _parent, _shift) \
49 GATE_MTK(_id, _name, _parent, &vdec3_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
H A Dclk-mt8183-ipu_conn.c44 #define GATE_IPU_CONN(_id, _name, _parent, _shift) \
45 GATE_MTK(_id, _name, _parent, &ipu_conn_cg_regs, _shift, \
48 #define GATE_IPU_CONN_APB(_id, _name, _parent, _shift) \
49 GATE_MTK(_id, _name, _parent, &ipu_conn_apb_cg_regs, _shift, \
52 #define GATE_IPU_CONN_AXI_I(_id, _name, _parent, _shift) \
53 GATE_MTK(_id, _name, _parent, &ipu_conn_axi_cg_regs, _shift, \
56 #define GATE_IPU_CONN_AXI1_I(_id, _name, _parent, _shift) \
57 GATE_MTK(_id, _name, _parent, &ipu_conn_axi1_cg_regs, _shift, \
60 #define GATE_IPU_CONN_AXI2_I(_id, _name, _parent, _shift) \
61 GATE_MTK(_id, _name, _parent,
[all...]
H A Dclk-mt8195-infra_ao.c44 #define GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, _flag) \
45 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \
48 #define GATE_INFRA_AO0(_id, _name, _parent, _shift) \
49 GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0)
51 #define GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, _flag) \
52 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao1_cg_regs, _shift, \
55 #define GATE_INFRA_AO1(_id, _name, _parent, _shift) \
56 GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0)
58 #define GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, _flag) \
59 GATE_MTK_FLAGS(_id, _name, _parent,
[all...]
H A Dclk-mt8188-infra_ao.c45 #define GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, _flag) \
46 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \
49 #define GATE_INFRA_AO0(_id, _name, _parent, _shift) \
50 GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0)
52 #define GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, _flag) \
53 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao1_cg_regs, _shift, \
56 #define GATE_INFRA_AO1(_id, _name, _parent, _shift) \
57 GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0)
59 #define GATE_INFRA_AO2(_id, _name, _parent, _shift) \
60 GATE_MTK(_id, _name, _parent,
[all...]
H A Dclk-mt8195-vdo1.c43 #define GATE_VDO1_0(_id, _name, _parent, _shift) \
44 GATE_MTK(_id, _name, _parent, &vdo1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
46 #define GATE_VDO1_1(_id, _name, _parent, _shift) \
47 GATE_MTK(_id, _name, _parent, &vdo1_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
49 #define GATE_VDO1_2(_id, _name, _parent, _shift) \
50 GATE_MTK(_id, _name, _parent, &vdo1_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
52 #define GATE_VDO1_2_FLAGS(_id, _name, _parent, _shift, _flags) \
53 GATE_MTK_FLAGS(_id, _name, _parent, &vdo1_2_cg_regs, _shift, \
56 #define GATE_VDO1_3(_id, _name, _parent, _shift) \
57 GATE_MTK(_id, _name, _parent,
[all...]
H A Dclk-mt8188-vdo1.c46 #define GATE_VDO1_0(_id, _name, _parent, _shift) \
47 GATE_MTK(_id, _name, _parent, &vdo1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
49 #define GATE_VDO1_1(_id, _name, _parent, _shift) \
50 GATE_MTK(_id, _name, _parent, &vdo1_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
52 #define GATE_VDO1_2(_id, _name, _parent, _shift) \
53 GATE_MTK(_id, _name, _parent, &vdo1_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
55 #define GATE_VDO1_3(_id, _name, _parent, _shift) \
56 GATE_MTK(_id, _name, _parent, &vdo1_3_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
58 #define GATE_VDO1_3_FLAGS(_id, _name, _parent, _shift, _flags) \
59 GATE_MTK_FLAGS(_id, _name, _parent,
[all...]
H A Dclk-mt8195-vdec.c31 #define GATE_VDEC0(_id, _name, _parent, _shift) \
32 GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
34 #define GATE_VDEC1(_id, _name, _parent, _shift) \
35 GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
37 #define GATE_VDEC2(_id, _name, _parent, _shift) \
38 GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
H A Dclk-mt8188-vdec.c32 #define GATE_VDEC0(_id, _name, _parent, _shift) \
33 GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
35 #define GATE_VDEC1(_id, _name, _parent, _shift) \
36 GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
38 #define GATE_VDEC2(_id, _name, _parent, _shift) \
39 GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
H A Dclk-mt7986-eth.c23 #define GATE_SGMII0(_id, _name, _parent, _shift) \
24 GATE_MTK(_id, _name, _parent, &sgmii0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
39 #define GATE_SGMII1(_id, _name, _parent, _shift) \
40 GATE_MTK(_id, _name, _parent, &sgmii1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
55 #define GATE_ETH(_id, _name, _parent, _shift) \
56 GATE_MTK(_id, _name, _parent, &eth_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
H A Dclk-mt8192-vdec.c33 #define GATE_VDEC0(_id, _name, _parent, _shift) \
34 GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
36 #define GATE_VDEC1(_id, _name, _parent, _shift) \
37 GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
39 #define GATE_VDEC2(_id, _name, _parent, _shift) \
40 GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
H A Dclk-mt8195-vdo0.c31 #define GATE_VDO0_0(_id, _name, _parent, _shift) \
32 GATE_MTK(_id, _name, _parent, &vdo0_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
34 #define GATE_VDO0_1(_id, _name, _parent, _shift) \
35 GATE_MTK(_id, _name, _parent, &vdo0_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
37 #define GATE_VDO0_2(_id, _name, _parent, _shift) \
38 GATE_MTK(_id, _name, _parent, &vdo0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
40 #define GATE_VDO0_2_FLAGS(_id, _name, _parent, _shift, _flags) \
41 GATE_MTK_FLAGS(_id, _name, _parent, &vdo0_2_cg_regs, _shift, \
H A Dclk-mt8188-vdo0.c34 #define GATE_VDO0_0(_id, _name, _parent, _shift) \
35 GATE_MTK(_id, _name, _parent, &vdo0_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
37 #define GATE_VDO0_1(_id, _name, _parent, _shift) \
38 GATE_MTK(_id, _name, _parent, &vdo0_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
40 #define GATE_VDO0_2(_id, _name, _parent, _shift) \
41 GATE_MTK(_id, _name, _parent, &vdo0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
43 #define GATE_VDO0_2_FLAGS(_id, _name, _parent, _shift, _flags) \
44 GATE_MTK_FLAGS(_id, _name, _parent, &vdo0_2_cg_regs, _shift, \
/linux-master/drivers/clk/starfive/
H A Dclk-starfive-jh71x0.h32 #define JH71X0_GATE(_idx, _name, _flags, _parent) \
37 .parents = { [0] = _parent }, \
40 #define JH71X0__DIV(_idx, _name, _max, _parent) \
45 .parents = { [0] = _parent }, \
48 #define JH71X0_GDIV(_idx, _name, _flags, _max, _parent) \
53 .parents = { [0] = _parent }, \
56 #define JH71X0_FDIV(_idx, _name, _parent) \
61 .parents = { [0] = _parent }, \
98 #define JH71X0__INV(_idx, _name, _parent) \
103 .parents = { [0] = _parent }, \
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