Searched refs:_id (Results 1 - 25 of 378) sorted by relevance

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/linux-master/include/linux/soc/pxa/
H A Dcpu.h61 unsigned int _id = (id) & 0xf3f0; \
62 _id == 0x2120; \
67 unsigned int _id = (id) & 0xf3ff; \
68 _id <= 0x2105; \
73 unsigned int _id = (id) & 0xffff; \
74 _id == 0x2d06; \
79 unsigned int _id = (id) & 0xf300; \
80 _id == 0x2100; \
92 unsigned int _id = (id) >> 4 & 0xfff; \
93 _id
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/linux-master/arch/powerpc/include/asm/
H A Dperf_event_server.h170 #define EVENT_VAR(_id, _suffix) event_attr_##_id##_suffix
171 #define EVENT_PTR(_id, _suffix) &EVENT_VAR(_id, _suffix).attr.attr
173 #define EVENT_ATTR(_name, _id, _suffix) \
174 PMU_EVENT_ATTR(_name, EVENT_VAR(_id, _suffix), _id, \
177 #define GENERIC_EVENT_ATTR(_name, _id) EVENT_ATTR(_name, _id, _g)
178 #define GENERIC_EVENT_PTR(_id) EVENT_PT
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/linux-master/drivers/clk/renesas/
H A Drcar-gen3-cpg.h37 #define DEF_GEN3_SDH(_name, _id, _parent, _offset) \
38 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SDH, _parent, .offset = _offset)
40 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \
41 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
43 #define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
44 DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \
48 #define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
50 DEF_GEN3_MDSEL(_name, _id, 12, _parent_sscg, _div_sscg, \
53 #define DEF_GEN3_OSC(_name, _id, _parent, _div) \
54 DEF_BASE(_name, _id, CLK_TYPE_GEN3_OS
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H A Drcar-gen4-cpg.h36 #define DEF_GEN4_SDH(_name, _id, _parent, _offset) \
37 DEF_BASE(_name, _id, CLK_TYPE_GEN4_SDH, _parent, .offset = _offset)
39 #define DEF_GEN4_SD(_name, _id, _parent, _offset) \
40 DEF_BASE(_name, _id, CLK_TYPE_GEN4_SD, _parent, .offset = _offset)
42 #define DEF_GEN4_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
43 DEF_BASE(_name, _id, CLK_TYPE_GEN4_MDSEL, \
47 #define DEF_GEN4_OSC(_name, _id, _parent, _div) \
48 DEF_BASE(_name, _id, CLK_TYPE_GEN4_OSC, _parent, .div = _div)
50 #define DEF_GEN4_Z(_name, _id, _type, _parent, _div, _offset) \
51 DEF_BASE(_name, _id, _typ
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H A Drzg2l-cpg.h129 #define DEF_TYPE(_name, _id, _type...) \
130 { .name = _name, .id = _id, .type = _type }
131 #define DEF_BASE(_name, _id, _type, _parent...) \
132 DEF_TYPE(_name, _id, _type, .parent = _parent)
133 #define DEF_SAMPLL(_name, _id, _parent, _conf) \
134 DEF_TYPE(_name, _id, CLK_TYPE_SAM_PLL, .parent = _parent, .conf = _conf)
135 #define DEF_G3S_PLL(_name, _id, _parent, _conf) \
136 DEF_TYPE(_name, _id, CLK_TYPE_G3S_PLL, .parent = _parent, .conf = _conf)
137 #define DEF_INPUT(_name, _id) \
138 DEF_TYPE(_name, _id, CLK_TYPE_I
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H A Drenesas-cpg-mssr.h44 #define DEF_TYPE(_name, _id, _type...) \
45 { .name = _name, .id = _id, .type = _type }
46 #define DEF_BASE(_name, _id, _type, _parent...) \
47 DEF_TYPE(_name, _id, _type, .parent = _parent)
49 #define DEF_INPUT(_name, _id) \
50 DEF_TYPE(_name, _id, CLK_TYPE_IN)
51 #define DEF_FIXED(_name, _id, _parent, _div, _mult) \
52 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
53 #define DEF_DIV6P1(_name, _id, _parent, _offset) \
54 DEF_BASE(_name, _id, CLK_TYPE_DIV6P
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/linux-master/drivers/net/wireless/intel/iwlwifi/fw/api/
H A Dcontext.h26 #define FW_CMD_ID_AND_COLOR(_id, _color) (((_id) << FW_CTXT_ID_POS) |\
/linux-master/drivers/clk/mediatek/
H A Dclk-mux.h41 #define __GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _paridx, \
45 .id = _id, \
62 #define GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
65 __GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
70 #define GATE_CLR_SET_UPD_FLAGS_INDEXED(_id, _name, _parents, _paridx, \
73 __GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
81 #define MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
84 GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
89 #define MUX_GATE_CLR_SET_UPD_FLAGS_INDEXED(_id, _name, _parents, \
92 GATE_CLR_SET_UPD_FLAGS_INDEXED(_id, _nam
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H A Dclk-mt8186-vdec.c39 #define GATE_VDEC0(_id, _name, _parent, _shift) \
40 GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
42 #define GATE_VDEC1(_id, _name, _parent, _shift) \
43 GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
45 #define GATE_VDEC2(_id, _name, _parent, _shift) \
46 GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
48 #define GATE_VDEC3(_id, _name, _parent, _shift) \
49 GATE_MTK(_id, _name, _parent, &vdec3_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
H A Dclk-mt8183-ipu_conn.c44 #define GATE_IPU_CONN(_id, _name, _parent, _shift) \
45 GATE_MTK(_id, _name, _parent, &ipu_conn_cg_regs, _shift, \
48 #define GATE_IPU_CONN_APB(_id, _name, _parent, _shift) \
49 GATE_MTK(_id, _name, _parent, &ipu_conn_apb_cg_regs, _shift, \
52 #define GATE_IPU_CONN_AXI_I(_id, _name, _parent, _shift) \
53 GATE_MTK(_id, _name, _parent, &ipu_conn_axi_cg_regs, _shift, \
56 #define GATE_IPU_CONN_AXI1_I(_id, _name, _parent, _shift) \
57 GATE_MTK(_id, _name, _parent, &ipu_conn_axi1_cg_regs, _shift, \
60 #define GATE_IPU_CONN_AXI2_I(_id, _name, _parent, _shift) \
61 GATE_MTK(_id, _nam
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H A Dclk-mtk.h37 #define GATE_DUMMY(_id, _name) { \
38 .id = _id, \
51 #define FIXED_CLK(_id, _name, _parent, _rate) { \
52 .id = _id, \
72 #define FACTOR_FLAGS(_id, _name, _parent, _mult, _div, _fl) { \
73 .id = _id, \
81 #define FACTOR(_id, _name, _parent, _mult, _div) \
82 FACTOR_FLAGS(_id, _name, _parent, _mult, _div, CLK_SET_RATE_PARENT)
112 #define MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, _shift, \
114 .id = _id, \
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H A Dclk-mt8195-infra_ao.c44 #define GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, _flag) \
45 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \
48 #define GATE_INFRA_AO0(_id, _name, _parent, _shift) \
49 GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0)
51 #define GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, _flag) \
52 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao1_cg_regs, _shift, \
55 #define GATE_INFRA_AO1(_id, _name, _parent, _shift) \
56 GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0)
58 #define GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, _flag) \
59 GATE_MTK_FLAGS(_id, _nam
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H A Dclk-mt8188-infra_ao.c45 #define GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, _flag) \
46 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \
49 #define GATE_INFRA_AO0(_id, _name, _parent, _shift) \
50 GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0)
52 #define GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, _flag) \
53 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao1_cg_regs, _shift, \
56 #define GATE_INFRA_AO1(_id, _name, _parent, _shift) \
57 GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0)
59 #define GATE_INFRA_AO2(_id, _name, _parent, _shift) \
60 GATE_MTK(_id, _nam
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H A Dclk-mt8195-vdo1.c43 #define GATE_VDO1_0(_id, _name, _parent, _shift) \
44 GATE_MTK(_id, _name, _parent, &vdo1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
46 #define GATE_VDO1_1(_id, _name, _parent, _shift) \
47 GATE_MTK(_id, _name, _parent, &vdo1_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
49 #define GATE_VDO1_2(_id, _name, _parent, _shift) \
50 GATE_MTK(_id, _name, _parent, &vdo1_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
52 #define GATE_VDO1_2_FLAGS(_id, _name, _parent, _shift, _flags) \
53 GATE_MTK_FLAGS(_id, _name, _parent, &vdo1_2_cg_regs, _shift, \
56 #define GATE_VDO1_3(_id, _name, _parent, _shift) \
57 GATE_MTK(_id, _nam
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H A Dclk-mt8188-vdo1.c46 #define GATE_VDO1_0(_id, _name, _parent, _shift) \
47 GATE_MTK(_id, _name, _parent, &vdo1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
49 #define GATE_VDO1_1(_id, _name, _parent, _shift) \
50 GATE_MTK(_id, _name, _parent, &vdo1_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
52 #define GATE_VDO1_2(_id, _name, _parent, _shift) \
53 GATE_MTK(_id, _name, _parent, &vdo1_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
55 #define GATE_VDO1_3(_id, _name, _parent, _shift) \
56 GATE_MTK(_id, _name, _parent, &vdo1_3_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
58 #define GATE_VDO1_3_FLAGS(_id, _name, _parent, _shift, _flags) \
59 GATE_MTK_FLAGS(_id, _nam
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H A Dclk-mt8195-vdec.c31 #define GATE_VDEC0(_id, _name, _parent, _shift) \
32 GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
34 #define GATE_VDEC1(_id, _name, _parent, _shift) \
35 GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
37 #define GATE_VDEC2(_id, _name, _parent, _shift) \
38 GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
H A Dclk-mt8188-vdec.c32 #define GATE_VDEC0(_id, _name, _parent, _shift) \
33 GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
35 #define GATE_VDEC1(_id, _name, _parent, _shift) \
36 GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
38 #define GATE_VDEC2(_id, _name, _parent, _shift) \
39 GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
/linux-master/drivers/staging/media/atomisp/include/media/
H A Dlm3554.h27 #define v4l2_queryctrl_entry_integer(_id, _name,\
31 .id = (_id), \
40 #define v4l2_queryctrl_entry_boolean(_id, _name,\
43 .id = (_id), \
53 #define s_ctrl_id_entry_integer(_id, _name, \
58 .qc = v4l2_queryctrl_entry_integer(_id, _name,\
65 #define s_ctrl_id_entry_boolean(_id, _name, \
69 .qc = v4l2_queryctrl_entry_boolean(_id, _name,\
/linux-master/drivers/interconnect/imx/
H A Dimx.h92 #define DEFINE_BUS_INTERCONNECT(_name, _id, _adj, ...) \
94 .id = _id, \
101 #define DEFINE_BUS_MASTER(_name, _id, _dest_id) \
102 DEFINE_BUS_INTERCONNECT(_name, _id, NULL, _dest_id)
104 #define DEFINE_BUS_SLAVE(_name, _id, _adj) \
105 DEFINE_BUS_INTERCONNECT(_name, _id, _adj)
/linux-master/drivers/clk/samsung/
H A Dclk.h44 #define ALIAS(_id, dname, a) \
46 .id = _id, \
69 #define FRATE(_id, cname, pname, f, frate) \
71 .id = _id, \
96 #define FFACTOR(_id, cname, pname, m, d, f) \
98 .id = _id, \
130 #define __MUX(_id, cname, pnames, o, s, w, f, mf) \
132 .id = _id, \
143 #define MUX(_id, cname, pnames, o, s, w) \
144 __MUX(_id, cnam
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/linux-master/include/linux/mfd/
H A Dcore.h17 #define MFD_CELL_ALL(_name, _res, _pdata, _pdsize, _id, _compat, _of_reg, _use_of_reg, _match) \
28 .id = (_id), \
31 #define MFD_CELL_OF_REG(_name, _res, _pdata, _pdsize, _id, _compat, _of_reg) \
32 MFD_CELL_ALL(_name, _res, _pdata, _pdsize, _id, _compat, _of_reg, true, NULL)
34 #define MFD_CELL_OF(_name, _res, _pdata, _pdsize, _id, _compat) \
35 MFD_CELL_ALL(_name, _res, _pdata, _pdsize, _id, _compat, 0, false, NULL)
37 #define MFD_CELL_ACPI(_name, _res, _pdata, _pdsize, _id, _match) \
38 MFD_CELL_ALL(_name, _res, _pdata, _pdsize, _id, NULL, 0, false, _match)
40 #define MFD_CELL_BASIC(_name, _res, _pdata, _pdsize, _id) \
41 MFD_CELL_ALL(_name, _res, _pdata, _pdsize, _id, NUL
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/linux-master/drivers/clk/pistachio/
H A Dclk.h19 #define GATE(_id, _name, _pname, _reg, _shift) \
21 .id = _id, \
39 #define MUX(_id, _name, _pnames, _reg, _shift) \
41 .id = _id, \
59 #define DIV(_id, _name, _pname, _reg, _width) \
61 .id = _id, \
69 #define DIV_F(_id, _name, _pname, _reg, _width, _div_flags) \
71 .id = _id, \
86 #define FIXED_FACTOR(_id, _name, _pname, _div) \
88 .id = _id, \
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/linux-master/drivers/regulator/
H A Dmax77541-regulator.c55 #define MAX77540_BUCK(_id, _ops) \
56 { .id = MAX77541_BUCK ## _id, \
57 .name = "buck"#_id, \
58 .of_match = "buck"#_id, \
61 .enable_mask = MAX77541_BIT_M ## _id ## _EN, \
66 .vsel_reg = MAX77541_REG_M ## _id ## _VOUT, \
68 .vsel_range_reg = MAX77541_REG_M ## _id ## _CFG1, \
74 #define MAX77541_BUCK(_id, _ops) \
75 { .id = MAX77541_BUCK ## _id, \
76 .name = "buck"#_id, \
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/linux-master/include/rdma/
H A Duverbs_std_types.h13 /* Returns _id, or causes a compile error if _id is not a u32.
19 #define _uobj_check_id(_id) ((_id) * typecheck(u32, _id))
24 #define uobj_get_read(_type, _id, _attrs) \
26 _uobj_check_id(_id), UVERBS_LOOKUP_READ, \
40 #define uobj_get_obj_read(_object, _type, _id, _attrs) \
42 uobj_get_read(_type, _id, _attrs)))
44 #define uobj_get_write(_type, _id, _attr
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/linux-master/include/linux/
H A Dmod_devicetable.h441 #define BCMA_CORE(_manuf, _id, _rev, _class) \
442 { .manuf = _manuf, .id = _id, .rev = _rev, .class = _class, }
616 #define MDIO_ID_ARGS(_id) \
617 ((_id)>>31) & 1, ((_id)>>30) & 1, ((_id)>>29) & 1, ((_id)>>28) & 1, \
618 ((_id)>>27) & 1, ((_id)>>26) & 1, ((_id)>>2
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