Searched refs:__raw_writew (Results 1 - 25 of 133) sorted by relevance

123456

/linux-master/arch/sh/include/mach-se/mach/
H A Dmrshpc.h13 __raw_writew(0x0674, MRSHPC_CPWCR); /* Card Vcc is 3.3v? */
15 __raw_writew(0x0678, MRSHPC_CPWCR); /* Card Vcc is 5V */
23 __raw_writew(0x8a84, MRSHPC_MW0CR1);
26 __raw_writew(0x0b00, MRSHPC_MW0CR2);
29 __raw_writew(0x0300, MRSHPC_MW0CR2);
32 __raw_writew(0x8a85, MRSHPC_MW1CR1);
35 __raw_writew(0x0a00, MRSHPC_MW1CR2);
38 __raw_writew(0x0200, MRSHPC_MW1CR2);
41 __raw_writew(0x8a86, MRSHPC_IOWCR1);
42 __raw_writew(
[all...]
/linux-master/arch/sh/boards/mach-se/7780/
H A Dirq.c24 __raw_writew(0, FPGA_INTMSK1);
26 __raw_writew((__raw_readw(FPGA_INTMSK1) | 0x0002), FPGA_INTMSK1);
28 __raw_writew(0, FPGA_INTMSK2);
32 __raw_writew( ((IRQPIN_SM501 << IRQPOS_SM501) |
36 __raw_writew(((IRQPIN_EXTINT4 << IRQPOS_EXTINT4) |
42 __raw_writew((IRQPIN_PCCPW << IRQPOS_PCCPW), FPGA_INTSEL3);
63 __raw_writew(0x0013, FPGA_PCI_INTSEL1);
64 __raw_writew(0xE402, FPGA_PCI_INTSEL2);
H A Dsetup.c75 __raw_writew( 'S' , PA_LED_DISP + (DISP_SEL0_ADDR << 1) );
76 __raw_writew( 'H' , PA_LED_DISP + (DISP_SEL1_ADDR << 1) );
77 __raw_writew( '-' , PA_LED_DISP + (DISP_SEL2_ADDR << 1) );
78 __raw_writew( 'L' , PA_LED_DISP + (DISP_SEL3_ADDR << 1) );
79 __raw_writew( 'i' , PA_LED_DISP + (DISP_SEL4_ADDR << 1) );
80 __raw_writew( 'n' , PA_LED_DISP + (DISP_SEL5_ADDR << 1) );
81 __raw_writew( 'u' , PA_LED_DISP + (DISP_SEL6_ADDR << 1) );
82 __raw_writew( 'x' , PA_LED_DISP + (DISP_SEL7_ADDR << 1) );
93 __raw_writew(0x0213, FPGA_REQSEL);
96 __raw_writew(
[all...]
/linux-master/arch/sh/boards/mach-sh7763rdp/
H A Dsetup.c169 __raw_writew((__raw_readw(PORT_PSEL2) & 0xFFC3), PORT_PSEL2);
171 __raw_writew(__raw_readw(PORT_PICR) & 0xFC0F, PORT_PICR);
174 __raw_writew(0x00, USB_USBHSC);
178 __raw_writew(__raw_readw(PORT_PJCR) & 0x0003, PORT_PJCR);
180 __raw_writew(__raw_readw(PORT_PICR) & 0xF3FF, PORT_PICR);
181 __raw_writew(0, PORT_PKCR);
182 __raw_writew(0, PORT_PLCR);
184 __raw_writew((__raw_readw(PORT_PSEL2) & 0x00C0), PORT_PSEL2);
186 __raw_writew((__raw_readw(PORT_PSEL3) & 0x0700), PORT_PSEL3);
190 __raw_writew((__raw_read
[all...]
/linux-master/arch/sh/boards/mach-se/770x/
H A Dirq.c100 __raw_writew(0, BCR_ILCRA);
101 __raw_writew(0, BCR_ILCRB);
102 __raw_writew(0, BCR_ILCRC);
103 __raw_writew(0, BCR_ILCRD);
104 __raw_writew(0, BCR_ILCRE);
105 __raw_writew(0, BCR_ILCRF);
106 __raw_writew(0, BCR_ILCRG);
/linux-master/arch/sh/boards/mach-se/7206/
H A Dirq.c39 __raw_writew(val, INTC_IPR01);
56 __raw_writew(msk0, INTMSK0);
57 __raw_writew(msk1, INTMSK1);
70 __raw_writew(val, INTC_IPR01);
88 __raw_writew(msk0, INTMSK0);
89 __raw_writew(msk1, INTMSK1);
115 __raw_writew(sts0, INTSTS0);
116 __raw_writew(sts1, INTSTS1);
143 __raw_writew(__raw_readw(INTC_ICR1) | 0x000b, INTC_ICR1); /* ICR1 */
146 __raw_writew(
[all...]
/linux-master/arch/sh/kernel/cpu/sh3/
H A Dserial-sh7710.c13 __raw_writew(__raw_readw(PACR) & 0xffc0, PACR);
14 __raw_writew(__raw_readw(PBCR) & 0x0fff, PBCR);
16 __raw_writew(__raw_readw(PBCR) & 0xf003, PBCR);
H A Dserial-sh7720.c17 __raw_writew((data & 0xfc03), PORT_PTCR);
21 __raw_writew((data & 0xfc03), PORT_PVCR);
27 __raw_writew((data & 0xffc3), PORT_PTCR);
31 __raw_writew((data & 0xffc3), PORT_PVCR);
H A Dserial-sh770x.c17 __raw_writew(data & 0x0fcf, SCPCR);
24 __raw_writew((data & 0x0fcf) | 0x1000, SCPCR);
/linux-master/arch/sh/boards/mach-se/7722/
H A Dsetup.c155 __raw_writew(0x010D, FPGA_OUT); /* FPGA */
157 __raw_writew(0x0000, PORT_PECR); /* PORT E 1 = IRQ5 ,E 0 = BS */
158 __raw_writew(0x1000, PORT_PJCR); /* PORT J 1 = IRQ1,J 0 =IRQ0 */
161 __raw_writew(0x0020, PORT_PSELD);
164 __raw_writew(0x0003, PORT_PSELB);
165 __raw_writew(0xe000, PORT_PSELC);
166 __raw_writew(0x0000, PORT_PKCR);
169 __raw_writew(0x4020, PORT_PHCR);
170 __raw_writew(0x0000, PORT_PLCR);
171 __raw_writew(
[all...]
/linux-master/arch/sh/boot/romimage/
H A Dmmcif-sh7724.c45 __raw_writew(0x0000, PTWCR);
48 __raw_writew(__raw_readw(PTXCR) & ~0x000f, PTXCR);
51 __raw_writew(__raw_readw(PSELA) & ~0x2000, PSELA);
54 __raw_writew(__raw_readw(PSELE) & ~0x3000, PSELE);
57 __raw_writew(__raw_readw(HIZCRC) & ~0x0620, HIZCRC);
60 __raw_writew(__raw_readw(DRVCRA) | 0x3000, DRVCRA);
/linux-master/arch/sh/boards/
H A Dboard-magicpanelr2.c101 __raw_writew(0x5555, PORT_PACR); /* 01 01 01 01 01 01 01 01 */
106 __raw_writew(0x5555, PORT_PBCR); /* 01 01 01 01 01 01 01 01 */
111 __raw_writew(0x5500, PORT_PCCR); /* 01 01 01 01 00 00 00 00 */
116 __raw_writew(0x5555, PORT_PDCR); /* 01 01 01 01 01 01 01 01 */
121 __raw_writew(0x3C00, PORT_PECR); /* 00 11 11 00 00 00 00 00 */
126 __raw_writew(0x0002, PORT_PFCR); /* 00 00 00 00 00 00 00 10 */
131 __raw_writew(0x03D5, PORT_PGCR); /* 00 00 00 11 11 01 01 01 */
136 __raw_writew(0x0050, PORT_PHCR); /* 00 00 00 00 01 01 00 00 */
141 __raw_writew(0x0000, PORT_PJCR); /* 00 00 00 00 00 00 00 00 */
146 __raw_writew(
[all...]
H A Dboard-polaris.c106 __raw_writew(wcr, WCR2);
111 __raw_writew(bcr_mask, BCR2);
142 __raw_writew(0, BCR_ILCRA);
143 __raw_writew(0, BCR_ILCRB);
144 __raw_writew(0, BCR_ILCRC);
145 __raw_writew(0, BCR_ILCRD);
146 __raw_writew(0, BCR_ILCRE);
147 __raw_writew(0, BCR_ILCRF);
148 __raw_writew(0, BCR_ILCRG);
H A Dboard-shmin.c21 __raw_writew(0x2a00, PFC_PHCR); // IRQ0-3=IRQ
22 __raw_writew(0x0aaa, INTC_ICR1); // IRQ0-3=IRQ-mode,Low-active.
/linux-master/arch/sh/boards/mach-highlander/
H A Dirq-r7785rp.c71 __raw_writew(0x0000, PA_IRLSSR1); /* FPGA IRLSSR1(CF_CD clear) */
74 __raw_writew(0x0000, PA_IRLPRA); /* FPGA IRLA */
75 __raw_writew(0xe598, PA_IRLPRB); /* FPGA IRLB */
76 __raw_writew(0x7060, PA_IRLPRC); /* FPGA IRLC */
77 __raw_writew(0x0000, PA_IRLPRD); /* FPGA IRLD */
78 __raw_writew(0x4321, PA_IRLPRE); /* FPGA IRLE */
79 __raw_writew(0xdcba, PA_IRLPRF); /* FPGA IRLF */
/linux-master/arch/sh/boards/mach-sdk7780/
H A Dirq.c37 __raw_writew(0xFFFF, FPGA_IRQ0MR);
39 __raw_writew(0x0003, FPGA_IMSR);
/linux-master/arch/m68k/coldfire/
H A Dpit.c48 __raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
49 __raw_writew(PIT_CYCLES_PER_JIFFY, TA(MCFPIT_PMR));
50 __raw_writew(MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE |
58 __raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
59 __raw_writew(MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE |
66 __raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
78 __raw_writew(delta, TA(MCFPIT_PMR));
105 __raw_writew(pcsr | MCFPIT_PCSR_PIF, TA(MCFPIT_PCSR));
/linux-master/arch/sh/boards/mach-se/7721/
H A Dsetup.c79 __raw_writew(0x0000, 0xA405010C); /* PGCR */
80 __raw_writew(0x0000, 0xA405010E); /* PHCR */
81 __raw_writew(0x00AA, 0xA4050118); /* PPCR */
82 __raw_writew(0x0000, 0xA4050124); /* PSELA */
/linux-master/arch/sh/boards/mach-se/7724/
H A Dirq.c75 __raw_writew(__raw_readw(set.mraddr) | 0x0001 << bit, set.mraddr);
83 __raw_writew(__raw_readw(set.mraddr) & ~(0x0001 << bit), set.mraddr);
116 __raw_writew(0xffff, IRQ0_MR); /* mask all */
117 __raw_writew(0xffff, IRQ1_MR); /* mask all */
118 __raw_writew(0xffff, IRQ2_MR); /* mask all */
119 __raw_writew(0x0000, IRQ0_SR); /* clear irq */
120 __raw_writew(0x0000, IRQ1_SR); /* clear irq */
121 __raw_writew(0x0000, IRQ2_SR); /* clear irq */
122 __raw_writew(0x002a, IRQ_MODE); /* set irq type */
/linux-master/arch/mips/alchemy/devboards/
H A Dbcsr.c67 __raw_writew(val, bcsr_regs[reg].raddr);
82 __raw_writew(r, bcsr_regs[reg].raddr);
104 __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR);
111 __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR);
112 __raw_writew(v, bcsr_virt + BCSR_REG_INTSTAT); /* ack */
119 __raw_writew(v, bcsr_virt + BCSR_REG_MASKSET);
135 __raw_writew(0xffff, bcsr_virt + BCSR_REG_MASKCLR);
136 __raw_writew(0xffff, bcsr_virt + BCSR_REG_INTSET);
137 __raw_writew(0xffff, bcsr_virt + BCSR_REG_INTSTAT);
/linux-master/arch/sh/boards/mach-hp6xx/
H A Dpm.c57 __raw_writew(frqcr, FRQCR);
65 __raw_writew(mcr & ~MCR_RFSH, MCR);
75 __raw_writew(0, RTCNT);
76 __raw_writew(mcr | MCR_RFSH | MCR_RMODE, MCR);
87 __raw_writew(frqcr, FRQCR);
90 __raw_writew(frqcr, FRQCR);
/linux-master/arch/sh/include/mach-ecovec24/mach/
H A Dromimage.h42 __raw_writew(__raw_readw(HIZCRA) & ~(1 << 1), HIZCRA);
/linux-master/arch/sh/kernel/cpu/sh4a/
H A Dserial-sh7722.c18 __raw_writew(data, PSCR);
/linux-master/arch/sparc/include/asm/
H A Dio.h20 #define writew_be(__l, __addr) __raw_writew(__l, __addr)
/linux-master/arch/sh/cchips/hd6446x/
H A Dhd64461.c29 __raw_writew(nimr, HD64461_NIMR);
40 __raw_writew(nimr, HD64461_NIMR);
86 __raw_writew(0x2240, INTC_ICR1);
88 __raw_writew(0xffff, HD64461_NIMR);

Completed in 304 milliseconds

123456