Searched refs:XE_REG_MCR (Results 1 - 7 of 7) sorted by relevance

/linux-master/drivers/gpu/drm/xe/regs/
H A Dxe_gt_regs.h61 #define XEHP_GLOBAL_MOCS(i) XE_REG_MCR(0x4000 + (i) * 4)
70 #define XEHP_TILE_ADDR_RANGE(_idx) XE_REG_MCR(0x4900 + (_idx) * 4)
71 #define XEHP_FLAT_CCS_BASE_ADDR XE_REG_MCR(0x4910)
73 #define WM_CHICKEN3 XE_REG_MCR(0x5588, XE_REG_OPTION_MASKED)
76 #define CHICKEN_RASTER_2 XE_REG_MCR(0x6208, XE_REG_OPTION_MASKED)
79 #define FF_MODE XE_REG_MCR(0x6210)
84 #define VFLSKPD XE_REG_MCR(0x62a8, XE_REG_OPTION_MASKED)
91 #define XEHP_FF_MODE2 XE_REG_MCR(0x6604)
106 #define XEHP_PSS_MODE2 XE_REG_MCR(0x703c, XE_REG_OPTION_MASKED)
109 #define XEHP_PSS_CHICKEN XE_REG_MCR(
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H A Dxe_reg_defs.h74 * To be used with XE_REG(). XE_REG_MCR() and XE_REG_INITIALIZER()
111 * XE_REG_MCR - Create a struct xe_reg_mcr from offset and additional flags
116 #define XE_REG_MCR(r_, ...) ((const struct xe_reg_mcr){ \ macro
/linux-master/drivers/gpu/drm/xe/tests/
H A Dxe_rtp_test.c26 #define MCR_REG1 XE_REG_MCR(1)
27 #define MCR_REG2 XE_REG_MCR(2)
28 #define MCR_REG3 XE_REG_MCR(3)
31 #undef XE_REG_MCR macro
32 #define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1) macro
/linux-master/drivers/gpu/drm/xe/
H A Dxe_tuning.c15 #undef XE_REG_MCR macro
16 #define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1) macro
H A Dxe_reg_whitelist.c16 #undef XE_REG_MCR macro
17 #define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1) macro
H A Dxe_pat.c166 struct xe_reg_mcr reg_mcr = XE_REG_MCR(_PAT_INDEX(i));
216 u32 pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i)));
249 u32 pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i)));
285 pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i)));
312 xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_ATS), xe2_pat_ats.value);
339 pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i)));
358 pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_PTA));
H A Dxe_wa.c93 #undef XE_REG_MCR macro
94 #define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1) macro

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