/linux-master/arch/xtensa/variants/test_kc705_be/include/variant/ |
H A D | tie.h | 76 * NOTE: caller must define the XCHAL_SA_REG macro (not defined here) 79 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize, 104 * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p) 116 XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \ 117 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \ 118 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \ 119 XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \ 120 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \ 121 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \ 122 XCHAL_SA_REG( [all...] |
/linux-master/arch/xtensa/variants/test_mmuhifi_c3/include/variant/ |
H A D | tie.h | 53 * NOTE: caller must define the XCHAL_SA_REG macro (not defined here) 56 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize, 81 * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p) 93 XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \ 94 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \ 95 XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) 102 XCHAL_SA_REG(s,0,0,1,0, ae_ovf_sar, 8, 4, 4,0x03F0, ur,240, 7,0,0,0) \ 103 XCHAL_SA_REG(s,0,0,1,0, ae_bithead, 4, 4, 4,0x03F1, ur,241, 32,0,0,0) \ 104 XCHAL_SA_REG(s,0,0,1,0,ae_ts_fts_bu_bp, 4, 4, 4,0x03F2, ur,242, 16,0,0,0) \ 105 XCHAL_SA_REG( [all...] |
/linux-master/arch/xtensa/variants/test_kc705_hifi/include/variant/ |
H A D | tie.h | 76 * NOTE: caller must define the XCHAL_SA_REG macro (not defined here) 79 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize, 104 * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p) 116 XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \ 117 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \ 118 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \ 119 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \ 120 XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \ 121 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \ 122 XCHAL_SA_REG( [all...] |
/linux-master/arch/xtensa/variants/de212/include/variant/ |
H A D | tie.h | 50 * NOTE: caller must define the XCHAL_SA_REG macro (not defined here) 53 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize, 78 * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p) 90 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \ 91 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \ 92 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \ 93 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \ 94 XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \ 95 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \ 96 XCHAL_SA_REG( [all...] |
/linux-master/arch/xtensa/variants/csp/include/variant/ |
H A D | tie.h | 73 * NOTE: caller must define the XCHAL_SA_REG macro (not defined here) 76 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize, 101 * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p) 113 XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \ 114 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \ 115 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \ 116 XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \ 117 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \ 118 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \ 119 XCHAL_SA_REG( [all...] |
/linux-master/arch/xtensa/variants/dc232b/include/variant/ |
H A D | tie.h | 54 * NOTE: caller must define the XCHAL_SA_REG macro (not defined here) 57 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize, 82 * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p) 94 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \ 95 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \ 96 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \ 97 XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \ 98 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \ 99 XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \ 100 XCHAL_SA_REG( [all...] |
/linux-master/arch/xtensa/variants/dc233c/include/variant/ |
H A D | tie.h | 73 * NOTE: caller must define the XCHAL_SA_REG macro (not defined here) 76 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize, 101 * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p) 113 XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \ 114 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \ 115 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \ 116 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \ 117 XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \ 118 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \ 119 XCHAL_SA_REG( [all...] |
/linux-master/arch/xtensa/include/asm/ |
H A D | coprocessor.h | 101 #define XCHAL_SA_REG(list,cc,abi,type,y,name,z,align,size,...) \ macro
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