| /haiku/src/add-ons/accelerants/s3/ |
| H A D | trio64_cursor.cpp | 23 WriteCrtcReg(0x45, bShow ? 0x01 : 0x00, 0x01);
48 WriteCrtcReg( 0x4e, xOffset );
49 WriteCrtcReg( 0x4f, yOffset );
51 WriteCrtcReg( 0x47, (x & 0xff) );
52 WriteCrtcReg( 0x46, (x & 0x0700) >> 8 );
54 WriteCrtcReg( 0x49, (y & 0xff) );
55 WriteCrtcReg( 0x48, (y & 0x0700) >> 8 );
96 WriteCrtcReg(0x4c, (0x0f00 & si.cursorOffset / 1024) >> 8);
97 WriteCrtcReg(0x4d, (0xff & si.cursorOffset / 1024));
102 WriteCrtcReg(
[all...] |
| H A D | virge_cursor.cpp | 23 WriteCrtcReg(0x45, bShow ? 0x01 : 0x00, 0x01);
48 WriteCrtcReg( 0x4e, xOffset );
49 WriteCrtcReg( 0x4f, yOffset );
51 WriteCrtcReg( 0x47, (x & 0xff) );
52 WriteCrtcReg( 0x46, (x & 0x0700) >> 8 );
54 WriteCrtcReg( 0x49, (y & 0xff) );
55 WriteCrtcReg( 0x48, (y & 0x0700) >> 8 );
96 WriteCrtcReg(0x4d, (0xff & si.cursorOffset / 1024));
97 WriteCrtcReg(0x4c, (0x0f00 & si.cursorOffset / 1024) >> 8);
102 WriteCrtcReg(
[all...] |
| H A D | savage_cursor.cpp | 40 WriteCrtcReg(0x45, bShow ? 0x01 : 0x00, 0x01);
71 WriteCrtcReg( 0x4e, xOffset );
72 WriteCrtcReg( 0x4f, yOffset );
74 WriteCrtcReg( 0x47, (x & 0xff) );
75 WriteCrtcReg( 0x46, (x & 0x0700) >> 8 );
77 WriteCrtcReg( 0x49, (y & 0xff) );
78 WriteCrtcReg( 0x48, (y & 0x0700) >> 8 );
128 WriteCrtcReg(0x4d, (0xff & si.cursorOffset / 1024));
129 WriteCrtcReg(0x4c, (0xff00 & si.cursorOffset / 1024) >> 8);
134 WriteCrtcReg(
[all...] |
| H A D | trio64_mode.cpp | 85 WriteCrtcReg(0x38, 0x48); // unlock sys regs
86 WriteCrtcReg(0x39, 0xa5); // unlock sys regs
89 WriteCrtcReg(0x45, 0x00, 0x01); // turn off hardware cursor
159 WriteCrtcReg(0x33, cr33);
160 WriteCrtcReg(0x50, cr50); // set number of bits per pixel & display width
161 WriteCrtcReg(0x67, pixmux); // set pixel format
179 WriteCrtcReg(0x11, 0x00, 0x80); // unlock CRTC reg's 0-7 by clearing bit 7 of cr11
182 WriteCrtcReg(k, crtc[k]);
185 WriteCrtcReg(0x3b, cr3b);
186 WriteCrtcReg(
[all...] |
| H A D | savage_mode.cpp | 67 WriteCrtcReg(0x69, 0x80, 0x80);
84 WriteCrtcReg(0x88, DISABLE_BLOCK_WRITE_2D, DISABLE_BLOCK_WRITE_2D);
113 WriteCrtcReg(0x69, 0x80, 0x80);
130 WriteCrtcReg(0x88, DISABLE_BLOCK_WRITE_2D, DISABLE_BLOCK_WRITE_2D);
146 WriteCrtcReg(0x67, 0x08, 0x08);
149 WriteCrtcReg(0x67, 0x08, 0x08);
153 WriteCrtcReg(MEMORY_CTRL0_REG, 0x00, MEM_PS1 + MEM_PS2);
185 WriteCrtcReg(0x78, 0xfb, 0xfb);
201 WriteCrtcReg(0x67, 0x08, 0x08);
204 WriteCrtcReg(
[all...] |
| H A D | trio64_init.cpp | 94 WriteCrtcReg(0x38, 0x48); // unlock sys regs
95 WriteCrtcReg(0x39, 0xa5); // unlock sys regs
97 WriteCrtcReg(0x40, 0x01, 0x01);
98 WriteCrtcReg(0x35, 0x00, 0x30);
99 WriteCrtcReg(0x33, 0x20, 0x72);
102 WriteCrtcReg(0x86, 0x80);
103 WriteCrtcReg(0x90, 0x00);
|
| H A D | virge_mode.cpp | 113 WriteCrtcReg(resetidx, tmp);
119 WriteCrtcReg(resetidx, tmp | 0x02);
123 WriteCrtcReg(resetidx, tmp & ~0x02);
128 WriteCrtcReg(resetidx, tmp);
154 WriteCrtcReg(regIndex, tmp | 0x02);
156 WriteCrtcReg(regIndex, tmp & ~0x02);
266 WriteCrtcReg(0x67, 0x00, 0x0c); // disable STREAMS processor
270 WriteCrtcReg(0x63, regRec.CR63);
271 WriteCrtcReg(0x66, regRec.CR66);
272 WriteCrtcReg(
[all...] |
| H A D | savage_edid.cpp | 46 WriteCrtcReg(index, value);
84 WriteCrtcReg(DDCPort, tmp | 0x13);
87 WriteCrtcReg(DDCPort, tmp);
|
| H A D | virge_edid.cpp | 45 WriteCrtcReg(index, value);
101 WriteCrtcReg(DDCPort, tmp | 0x13);
105 WriteCrtcReg(DDCPort, tmp);
|
| H A D | register_io.h | 46 void WriteCrtcReg(uint8 index, uint8 value);
47 void WriteCrtcReg(uint8 index, uint8 value, uint8 mask);
|
| H A D | savage_init.cpp | 161 WriteCrtcReg(0x40, 0x01, 0x01);
163 WriteCrtcReg(0x11, 0x00, 0x80); // unlock CRTC reg's 0-7 by clearing bit 7 of cr11
164 WriteCrtcReg(0x38, 0x48); // unlock sys regs CR20~CR3F
165 WriteCrtcReg(0x39, 0xa0); // unlock sys regs CR40~CRFF
168 WriteCrtcReg(0x40, 0x00, 0x01);
169 WriteCrtcReg(0x38, 0x48); // unlock sys regs CR20~CR3F
252 WriteCrtcReg(0x66, 0x02, 0x02); // set reset flag
254 WriteCrtcReg(0x66, 0x00, 0x02); // clear reset flag
|
| H A D | register_io.cpp | 134 void WriteCrtcReg(uint8 index, uint8 value) function
146 void WriteCrtcReg(uint8 index, uint8 value, uint8 mask) function
|
| H A D | virge_init.cpp | 102 WriteCrtcReg(0x40, 0x01, 0x01);
|
| /haiku/src/add-ons/accelerants/intel_810/ |
| H A D | i810_mode.cpp | 148 WriteCrtcReg(0x11, crtc[0x11] & ~0x80);
151 WriteCrtcReg(j, crtc[j]);
155 WriteCrtcReg(EXT_VERT_TOTAL, vTotal >> 8);
156 WriteCrtcReg(EXT_VERT_DISPLAY, vDisp_e >> 8);
157 WriteCrtcReg(EXT_VERT_SYNC_START, vSync_s >> 8);
158 WriteCrtcReg(EXT_VERT_BLANK_START, vBlank_s >> 8);
159 WriteCrtcReg(EXT_HORIZ_TOTAL, hTotal >> 8);
160 WriteCrtcReg(EXT_HORIZ_BLANK, (hBlank_e & 0x40) >> 6);
161 WriteCrtcReg(EXT_OFFSET, offset >> 8);
163 WriteCrtcReg(INTERLACE_CNT
[all...] |
| H A D | i810_regs.h | 134 WriteCrtcReg(uint8 index, uint8 value) function
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| /haiku/src/add-ons/accelerants/3dfx/ |
| H A D | 3dfx_mode.cpp | 89 WriteCrtcReg(uint8 index, uint8 value) function
331 WriteCrtcReg(j, crtc[j]);
333 WriteCrtcReg(0x1a, cr1a);
334 WriteCrtcReg(0x1b, cr1b);
|