Searched refs:WREG32_PLL_P (Results 1 - 5 of 5) sorted by relevance
| /linux-master/drivers/gpu/drm/radeon/ |
| H A D | radeon_legacy_crtc.c | 234 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
261 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
864 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
868 WREG32_PLL_P(RADEON_P2PLL_CNTL,
876 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
880 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
884 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
893 WREG32_PLL_P(RADEON_P2PLL_CNTL,
912 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
945 WREG32_PLL_P(RADEON_VCLK_ECP_CNT
[all...] |
| H A D | radeon_legacy_tv.c | 758 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVCLK_SRC_SEL_TVPLL);
760 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVPLL_RESET, ~RADEON_TVPLL_RESET);
764 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_RESET);
769 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~0xf);
770 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVCLK_SRC_SEL_TVPLL, ~RADEON_TVCLK_SRC_SEL_TVPLL);
772 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, (1 << RADEON_TVPDC_SHIFT), ~RADEON_TVPDC_MASK);
773 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_SLEEP);
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| H A D | radeon_legacy_encoders.c | 121 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
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| H A D | radeon.h | 2541 #define WREG32_PLL_P(reg, val, mask) \ macro
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| /linux-master/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu.h | 1305 #define WREG32_PLL_P(reg, val, mask) \ macro
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