Searched refs:WREG32 (Results 1 - 25 of 183) sorted by relevance

12345678

/linux-master/drivers/accel/habanalabs/goya/
H A Dgoya_security.c23 WREG32(pb_addr, 0);
81 WREG32(pb_addr + word_offset, ~mask);
104 WREG32(pb_addr + word_offset, ~mask);
128 WREG32(pb_addr + word_offset, ~mask);
160 WREG32(pb_addr + word_offset, ~mask);
180 WREG32(pb_addr + word_offset, ~mask);
194 WREG32(pb_addr + word_offset, ~mask);
210 WREG32(pb_addr + word_offset, ~mask);
228 WREG32(pb_addr + word_offset, ~mask);
251 WREG32(pb_add
[all...]
H A Dgoya_coresight.c243 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);
251 WREG32(base_reg + 0xE80, 0x80004);
252 WREG32(base_reg + 0xD64, 7);
253 WREG32(base_reg + 0xD60, 0);
254 WREG32(base_reg + 0xD00, lower_32_bits(input->he_mask));
255 WREG32(base_reg + 0xD20, lower_32_bits(input->sp_mask));
256 WREG32(base_reg + 0xD60, 1);
257 WREG32(base_reg + 0xD00, upper_32_bits(input->he_mask));
258 WREG32(base_reg + 0xD20, upper_32_bits(input->sp_mask));
259 WREG32(base_re
[all...]
H A Dgoya.c732 WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_FULLY_TRUSTED);
734 WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_PARTLY_TRUSTED);
893 WREG32(mmMMU_LOG2_DDR_SIZE, ilog2(prop->dram_size));
1104 WREG32(mmDMA_QM_0_PQ_BASE_LO + reg_off, lower_32_bits(bus_address));
1105 WREG32(mmDMA_QM_0_PQ_BASE_HI + reg_off, upper_32_bits(bus_address));
1107 WREG32(mmDMA_QM_0_PQ_SIZE + reg_off, ilog2(HL_QUEUE_LENGTH));
1108 WREG32(mmDMA_QM_0_PQ_PI + reg_off, 0);
1109 WREG32(mmDMA_QM_0_PQ_CI + reg_off, 0);
1111 WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
1112 WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_H
[all...]
/linux-master/drivers/gpu/drm/radeon/
H A Dvce_v2_0.c46 WREG32(VCE_CLOCK_GATING_B, tmp);
50 WREG32(VCE_UENC_CLOCK_GATING, tmp);
54 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
56 WREG32(VCE_CGTT_CLK_OVERRIDE, 0);
61 WREG32(VCE_CLOCK_GATING_B, tmp);
66 WREG32(VCE_UENC_CLOCK_GATING, tmp);
70 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
86 WREG32(VCE_CLOCK_GATING_B, tmp);
92 WREG32(VCE_UENC_CLOCK_GATING, tmp);
97 WREG32(VCE_UENC_REG_CLOCK_GATIN
[all...]
H A Drv515.c136 WREG32(R_000300_VGA_RENDER_CONTROL,
201 WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
203 WREG32(MC_IND_INDEX, 0);
214 WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
215 WREG32(MC_IND_DATA, (v));
216 WREG32(MC_IND_INDEX, 0);
276 WREG32(R_000300_VGA_RENDER_CONTROL, 0);
285 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
287 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
288 WREG32(AVIVO_D1CRTC_UPDATE_LOC
[all...]
H A Duvd_v4_2.c52 WREG32(UVD_VCPU_CACHE_OFFSET0, addr);
53 WREG32(UVD_VCPU_CACHE_SIZE0, size);
57 WREG32(UVD_VCPU_CACHE_OFFSET1, addr);
58 WREG32(UVD_VCPU_CACHE_SIZE1, size);
63 WREG32(UVD_VCPU_CACHE_OFFSET2, addr);
64 WREG32(UVD_VCPU_CACHE_SIZE2, size);
68 WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));
72 WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
75 WREG32(UVD_GP_SCRATCH4, rdev->uvd.max_handles);
H A Dradeon_bios.c266 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
269 WREG32(AVIVO_D1VGA_CONTROL,
272 WREG32(AVIVO_D2VGA_CONTROL,
275 WREG32(AVIVO_VGA_RENDER_CONTROL,
278 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
283 WREG32(R600_BUS_CNTL, bus_cntl);
285 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
286 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
287 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
289 WREG32(R600_ROM_CNT
[all...]
H A Duvd_v1_0.c70 WREG32(UVD_RBC_RB_WPTR, ring->wptr);
123 WREG32(UVD_VCPU_CACHE_OFFSET0, addr);
124 WREG32(UVD_VCPU_CACHE_SIZE0, size);
128 WREG32(UVD_VCPU_CACHE_OFFSET1, addr);
129 WREG32(UVD_VCPU_CACHE_SIZE1, size);
134 WREG32(UVD_VCPU_CACHE_OFFSET2, addr);
135 WREG32(UVD_VCPU_CACHE_SIZE2, size);
139 WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));
143 WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
145 WREG32(UVD_FW_STAR
[all...]
H A Dvce_v1_0.c98 WREG32(VCE_RB_WPTR, ring->wptr);
100 WREG32(VCE_RB_WPTR2, ring->wptr);
110 WREG32(VCE_CLOCK_GATING_A, tmp);
115 WREG32(VCE_UENC_CLOCK_GATING, tmp);
119 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
123 WREG32(VCE_CLOCK_GATING_A, tmp);
128 WREG32(VCE_UENC_CLOCK_GATING, tmp);
132 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
142 WREG32(VCE_CLOCK_GATING_A, tmp);
147 WREG32(VCE_CLOCK_GATING_
[all...]
H A Dradeon_dp_auxch.c101 WREG32(chan->rec.mask_clk_reg, tmp);
110 WREG32(AUX_CONTROL + aux_offset[instance], tmp);
113 WREG32(AUX_SW_CONTROL + aux_offset[instance],
115 WREG32(AUX_SW_CONTROL + aux_offset[instance],
121 WREG32(AUX_SW_DATA + aux_offset[instance],
125 WREG32(AUX_SW_DATA + aux_offset[instance],
129 WREG32(AUX_SW_DATA + aux_offset[instance],
133 WREG32(AUX_SW_DATA + aux_offset[instance],
139 WREG32(AUX_SW_DATA + aux_offset[instance],
145 WREG32(AUX_SW_INTERRUPT_CONTRO
[all...]
H A Devergreen_hdmi.c66 WREG32(AZ_HOT_PLUG_CONTROL, tmp);
82 WREG32(HDMI_ACR_PACKET_CONTROL + offset,
85 WREG32(HDMI_ACR_PACKET_CONTROL + offset,
89 WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr->cts_32khz));
90 WREG32(HDMI_ACR_32_1 + offset, acr->n_32khz);
92 WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr->cts_44_1khz));
93 WREG32(HDMI_ACR_44_1 + offset, acr->n_44_1khz);
95 WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr->cts_48khz));
96 WREG32(HDMI_ACR_48_1 + offset, acr->n_48khz);
215 WREG32(AFMT_AVI_INFO
[all...]
H A Dradeon_i2c.c112 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
115 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
126 WREG32(rec->mask_clk_reg, temp);
131 WREG32(rec->a_clk_reg, temp);
134 WREG32(rec->a_data_reg, temp);
138 WREG32(rec->en_clk_reg, temp);
141 WREG32(rec->en_data_reg, temp);
145 WREG32(rec->mask_clk_reg, temp);
149 WREG32(rec->mask_data_reg, temp);
164 WREG32(re
[all...]
H A Dradeon_cursor.c44 WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
51 WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
58 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock);
99 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
101 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
103 WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset);
104 WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN |
110 WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH,
113 WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH,
117 WREG32(AVIVO_D1CUR_SURFACE_ADDRES
[all...]
H A Dr600.c125 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
136 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
137 WREG32(R600_RCU_DATA, (v));
147 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
158 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
159 WREG32(R600_UVD_CTX_DATA, (v));
345 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
872 WREG32(DC_HPD1_INT_CONTROL, tmp);
880 WREG32(DC_HPD2_INT_CONTROL, tmp);
888 WREG32(DC_HPD3_INT_CONTRO
[all...]
H A Drv770.c809 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
812 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset,
815 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset,
819 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
820 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
822 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
823 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
825 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
827 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
840 WREG32(AVIVO_D1GRPH_UPDAT
[all...]
/linux-master/drivers/accel/habanalabs/gaudi/
H A Dgaudi_coresight.c405 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);
413 WREG32(base_reg + 0xE80, 0x80004);
414 WREG32(base_reg + 0xD64, 7);
415 WREG32(base_reg + 0xD60, 0);
416 WREG32(base_reg + 0xD00, lower_32_bits(input->he_mask));
417 WREG32(base_reg + 0xD60, 1);
418 WREG32(base_reg + 0xD00, upper_32_bits(input->he_mask));
419 WREG32(base_reg + 0xE70, 0x10);
420 WREG32(base_reg + 0xE60, 0);
421 WREG32(base_re
[all...]
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dvce_v2_0.c94 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
96 WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
144 WREG32(mmVCE_CGTT_CLK_OVERRIDE, 7);
155 WREG32(mmVCE_CLOCK_GATING_A, tmp);
160 WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
165 WREG32(mmVCE_CLOCK_GATING_B, tmp);
175 WREG32(mmVCE_CLOCK_GATING_B, 0xf7);
177 WREG32(mmVCE_LMI_CTRL, 0x00398000);
179 WREG32(mmVCE_LMI_SWAP_CNTL, 0);
180 WREG32(mmVCE_LMI_SWAP_CNTL
[all...]
H A Dsi_ih.c42 WREG32(IH_CNTL, ih_cntl);
43 WREG32(IH_RB_CNTL, ih_rb_cntl);
54 WREG32(IH_RB_CNTL, ih_rb_cntl);
55 WREG32(IH_CNTL, ih_cntl);
56 WREG32(IH_RB_RPTR, 0);
57 WREG32(IH_RB_WPTR, 0);
70 WREG32(INTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
74 WREG32(INTERRUPT_CNTL, interrupt_cntl);
76 WREG32(IH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
84 WREG32(IH_RB_WPTR_ADDR_L
[all...]
H A Dcik_ih.c67 WREG32(mmIH_CNTL, ih_cntl);
68 WREG32(mmIH_RB_CNTL, ih_rb_cntl);
86 WREG32(mmIH_RB_CNTL, ih_rb_cntl);
87 WREG32(mmIH_CNTL, ih_cntl);
89 WREG32(mmIH_RB_RPTR, 0);
90 WREG32(mmIH_RB_WPTR, 0);
116 WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
124 WREG32(mmINTERRUPT_CNTL, interrupt_cntl);
126 WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
136 WREG32(mmIH_RB_WPTR_ADDR_L
[all...]
H A Damdgpu_amdkfd_gfx_v7.c54 WREG32(mmSRBM_GFX_CNTL, value);
59 WREG32(mmSRBM_GFX_CNTL, 0);
85 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
86 WREG32(mmSH_MEM_APE1_BASE, sh_mem_ape1_base);
87 WREG32(mmSH_MEM_APE1_LIMIT, sh_mem_ape1_limit);
88 WREG32(mmSH_MEM_BASES, sh_mem_bases);
105 WREG32(mmATC_VMID0_PASID_MAPPING + vmid, pasid_mapping);
109 WREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid);
112 WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping);
128 WREG32(mmCPC_INT_CNT
[all...]
H A Dgmc_v6_0.c73 WREG32(mmBIF_FB_EN, 0);
77 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
91 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
95 WREG32(mmBIF_FB_EN, tmp);
173 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
174 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
178 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
179 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
183 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
186 WREG32(mmMC_SEQ_SUP_CNT
[all...]
H A Dgmc_v8_0.c179 WREG32(mmBIF_FB_EN, 0);
183 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
196 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
200 WREG32(mmBIF_FB_EN, tmp);
241 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, ixMC_IO_DEBUG_UP_159);
309 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
310 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
314 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
315 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
319 WREG32(mmMC_SEQ_SUP_PG
[all...]
H A Duvd_v5_0.c88 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
287 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
289 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
294 WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
295 WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
299 WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3);
300 WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
305 WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);
306 WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
308 WREG32(mmUVD_UDEC_ADDR_CONFI
[all...]
H A Dvce_v3_0.c85 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));
87 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));
96 WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);
117 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));
119 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));
128 WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);
148 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));
150 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));
153 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
155 WREG32(mmVCE_RB_WPTR
[all...]
H A Damdgpu_amdkfd_arcturus.c138 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
153 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET,
158 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);
159 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR,
161 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI,
164 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1);
166 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
168 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
171 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
173 WREG32(sdma_rlc_reg_offse
[all...]

Completed in 347 milliseconds

12345678