Lines Matching refs:WREG32
98 WREG32(VCE_RB_WPTR, ring->wptr);
100 WREG32(VCE_RB_WPTR2, ring->wptr);
110 WREG32(VCE_CLOCK_GATING_A, tmp);
115 WREG32(VCE_UENC_CLOCK_GATING, tmp);
119 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
123 WREG32(VCE_CLOCK_GATING_A, tmp);
128 WREG32(VCE_UENC_CLOCK_GATING, tmp);
132 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
142 WREG32(VCE_CLOCK_GATING_A, tmp);
147 WREG32(VCE_CLOCK_GATING_B, tmp);
151 WREG32(VCE_UENC_CLOCK_GATING, tmp);
155 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
225 WREG32(VCE_CLOCK_GATING_B, 0);
229 WREG32(VCE_LMI_CTRL, 0x00398000);
231 WREG32(VCE_LMI_SWAP_CNTL, 0);
232 WREG32(VCE_LMI_SWAP_CNTL1, 0);
233 WREG32(VCE_LMI_VM_CTRL, 0);
235 WREG32(VCE_VCPU_SCRATCH7, RADEON_MAX_VCE_HANDLES);
239 WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);
240 WREG32(VCE_VCPU_CACHE_SIZE0, size);
244 WREG32(VCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff);
245 WREG32(VCE_VCPU_CACHE_SIZE1, size);
249 WREG32(VCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff);
250 WREG32(VCE_VCPU_CACHE_SIZE2, size);
254 WREG32(VCE_LMI_FW_START_KEYSEL, rdev->vce.keyselect);
298 WREG32(VCE_RB_RPTR, ring->wptr);
299 WREG32(VCE_RB_WPTR, ring->wptr);
300 WREG32(VCE_RB_BASE_LO, ring->gpu_addr);
301 WREG32(VCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
302 WREG32(VCE_RB_SIZE, ring->ring_size / 4);
305 WREG32(VCE_RB_RPTR2, ring->wptr);
306 WREG32(VCE_RB_WPTR2, ring->wptr);
307 WREG32(VCE_RB_BASE_LO2, ring->gpu_addr);
308 WREG32(VCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
309 WREG32(VCE_RB_SIZE2, ring->ring_size / 4);