Searched refs:WR (Results 1 - 13 of 13) sorted by relevance

/linux-master/drivers/ata/pata_parport/
H A Dbpck.c93 #define WR(r,v) bpck_write_regr(pi,2,r,v) macro
103 WR(4, 0x40);
109 WR(4, 0);
113 WR(4, 0x50);
119 WR(4, 0x10);
123 WR(4, 0x48);
128 WR(4, 8);
132 WR(4, 0x48);
137 WR(4, 8);
141 WR(
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H A Depia.c94 #define WR(r, v) epia_write_regr(pi, 0, r, v) macro
114 WR(0x86, 8);
119 /* WR(0x84,0x10); */
167 WR(0x84, 3);
171 w2(4); WR(0x84, 0);
175 WR(0x84, 3);
179 w2(4); WR(0x84, 0);
183 WR(0x84, 3);
187 w2(4); WR(0x84, 0);
215 WR(
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H A Depat.c208 #define WR(r, v) epat_write_regr(pi, 2, r, v) macro
237 WR(0x8, 0x12);
238 WR(0xc, 0x14);
239 WR(0x12, 0x10);
240 WR(0xe, 0xf);
241 WR(0xf, 4);
242 /* WR(0xe,0xa);WR(0xf,4); */
243 WR(0xe, 0xd);
244 WR(
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/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dsddr2.c63 int CL, WR, DLL = 0, ODT = 0; local
68 WR = ram->next->bios.timing_10_WR;
74 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16;
87 WR = ramxlat(ramddr2_wr, WR);
88 if (CL < 0 || WR < 0)
92 ram->mr[0] |= (WR & 0x07) << 9;
H A Dgddr3.c73 int CL, WR, CWL, DLL = 0, ODT = 0, RON, hi; local
79 WR = ram->next->bios.timing_10_WR;
87 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16;
103 WR = ramxlat(ramgddr3_wr_lo, WR);
104 if (CL < 0 || CWL < 1 || CWL > 7 || WR < 0)
115 ram->mr[1] |= (WR & 0x03) << 4;
116 ram->mr[1] |= (WR & 0x04) << 5;
H A Dsddr3.c72 int CWL, CL, WR, DLL = 0, ODT = 0; local
84 WR = ram->next->bios.timing_10_WR;
90 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16;
102 WR = ramxlat(ramddr3_wr, WR);
103 if (CL < 0 || CWL < 0 || WR < 0)
107 ram->mr[0] |= (WR & 0x07) << 9;
H A Dgddr5.c38 int WL, CL, WR, at[2], dt, ds; local
60 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16;
70 if (WL < 1 || WL > 7 || CL < 5 || CL > 36 || WR < 4 || WR > 35)
73 WR -= 4;
76 ram->mr[0] |= (WR & 0x0f) << 8;
118 ram->mr[8] |= (WR & 0x10) >> 3;
H A Dramnv50.c110 timing[1] = (T(WR) + 1 + T(CWL)) << 24 |
176 T(WR) = ((timing[1] >> 24) & 0xff) - 1 - T(CWL);
H A Dramgt215.c375 timing[1] = (T(WR) + 1 + T(CWL)) << 24 |
/linux-master/drivers/i2c/busses/
H A Di2c-au1550.c44 static inline void WR(struct i2c_au1550_data *a, int r, unsigned long v) function
105 WR(adap, PSC_SMBEVNT, PSC_SMBEVNT_ALLCLR);
108 WR(adap, PSC_SMBPCR, PSC_SMBPCR_DC);
124 WR(adap, PSC_SMBTXRX, addr);
125 WR(adap, PSC_SMBPCR, PSC_SMBPCR_MS);
169 WR(adap, PSC_SMBTXRX, 0);
177 WR(adap, PSC_SMBTXRX, PSC_SMBTXRX_STP);
197 WR(adap, PSC_SMBTXRX, data);
206 WR(adap, PSC_SMBTXRX, data);
219 WR(ada
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/linux-master/include/linux/ceph/
H A Drados.h228 f(WRITE, __CEPH_OSD_OP(WR, DATA, 1), "write") \
229 f(WRITEFULL, __CEPH_OSD_OP(WR, DATA, 2), "writefull") \
230 f(TRUNCATE, __CEPH_OSD_OP(WR, DATA, 3), "truncate") \
231 f(ZERO, __CEPH_OSD_OP(WR, DATA, 4), "zero") \
232 f(DELETE, __CEPH_OSD_OP(WR, DATA, 5), "delete") \
235 f(APPEND, __CEPH_OSD_OP(WR, DATA, 6), "append") \
236 f(SETTRUNC, __CEPH_OSD_OP(WR, DATA, 8), "settrunc") \
237 f(TRIMTRUNC, __CEPH_OSD_OP(WR, DATA, 9), "trimtrunc") \
240 f(TMAPPUT, __CEPH_OSD_OP(WR, DATA, 11), "tmapput") \
243 f(CREATE, __CEPH_OSD_OP(WR, DAT
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/linux-master/sound/soc/au1x/
H A Dac97c.c77 static inline void WR(struct au1xpsc_audio_data *ctx, int reg, unsigned long v) function
103 WR(ctx, AC97_CMDRESP, CMD_IDX(r) | CMD_READ);
142 WR(ctx, AC97_CMDRESP, CMD_WRITE | CMD_IDX(r) | CMD_SET_DATA(v));
159 WR(ctx, AC97_CONFIG, ctx->cfg | CFG_SG | CFG_SN);
161 WR(ctx, AC97_CONFIG, ctx->cfg | CFG_SG);
162 WR(ctx, AC97_CONFIG, ctx->cfg);
170 WR(ctx, AC97_CONFIG, ctx->cfg | CFG_RS);
172 WR(ctx, AC97_CONFIG, ctx->cfg);
267 WR(ctx, AC97_ENABLE, EN_D | EN_CE);
268 WR(ct
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H A Di2sc.c75 static inline void WR(struct au1xpsc_audio_data *ctx, int reg, unsigned long v) function
146 WR(ctx, I2S_ENABLE, EN_D | EN_CE);
147 WR(ctx, I2S_ENABLE, EN_CE);
149 WR(ctx, I2S_CFG, ctx->cfg);
154 WR(ctx, I2S_CFG, ctx->cfg);
155 WR(ctx, I2S_ENABLE, EN_D); /* power off */
279 WR(ctx, I2S_ENABLE, EN_D); /* clock off, disable */
287 WR(ctx, I2S_ENABLE, EN_D); /* clock off, disable */

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