Searched refs:VIASR (Results 1 - 12 of 12) sorted by relevance

/linux-master/drivers/video/fbdev/via/
H A Dvia_clock.c44 via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */
45 via_write_reg(VIASR, 0x46, data & 0xFF);
46 via_write_reg(VIASR, 0x47, (data >> 8) & 0xFF);
47 via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */
52 via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */
53 via_write_reg(VIASR, 0x44, data & 0xFF);
54 via_write_reg(VIASR, 0x45, (data >> 8) & 0xFF);
55 via_write_reg(VIASR, 0x46, (data >> 16) & 0xFF);
56 via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */
61 via_write_reg_mask(VIASR,
[all...]
H A Dviamode.c11 struct io_reg CN400_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
12 {VIASR, SR15, 0x02, 0x02},
13 {VIASR, SR16, 0xBF, 0x08},
14 {VIASR, SR17, 0xFF, 0x1F},
15 {VIASR, SR18, 0xFF, 0x4E},
16 {VIASR, SR1A, 0xFB, 0x08},
17 {VIASR, SR1E, 0x0F, 0x01},
18 {VIASR, SR2A, 0xFF, 0x00},
44 struct io_reg CN700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
45 {VIASR, SR1
[all...]
H A Ddvi.c44 sr2a = viafb_read_reg(VIASR, SR2A);
45 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
51 sr2a = viafb_read_reg(VIASR, SR2A);
52 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
54 sr1e = viafb_read_reg(VIASR, SR1E);
55 viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT6 + BIT7);
60 sr1e = viafb_read_reg(VIASR, SR1E);
61 viafb_write_reg_mask(SR1E, VIASR, 0xF0, BIT4 +
65 sr3e = viafb_read_reg(VIASR, SR3E);
66 viafb_write_reg_mask(SR3E, VIASR,
[all...]
H A Dvia_utility.c138 viafb_write_reg_mask(SR16, VIASR, 0x80, BIT7);
151 sr1a = (unsigned int)viafb_read_reg(VIASR, SR1A);
152 viafb_write_reg_mask(SR1A, VIASR, 0x0, BIT0);
169 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0);
180 viafb_write_reg(SR1A, VIASR, sr1a);
193 viafb_write_reg_mask(SR16, VIASR, 0x80, BIT7);
206 sr1a = viafb_read_reg(VIASR, SR1A);
207 viafb_write_reg_mask(SR1A, VIASR, 0x0, BIT0);
219 viafb_write_reg(SR1A, VIASR, sr1a);
H A Dvia-gpio.c31 .vg_io_port = VIASR,
37 .vg_io_port = VIASR,
43 .vg_io_port = VIASR,
49 .vg_io_port = VIASR,
55 .vg_io_port = VIASR,
61 .vg_io_port = VIASR,
94 reg = via_read_reg(VIASR, gpio->vg_port_index);
100 via_write_reg(VIASR, gpio->vg_port_index, reg);
123 via_write_reg_mask(VIASR, gpio->vg_port_index, 0,
138 reg = via_read_reg(VIASR, gpi
[all...]
H A Dhw.c668 viafb_write_reg_mask(0x1A, VIASR, 0x00, 0x01);
674 viafb_write_reg_mask(0x1A, VIASR, 0x01, 0x01);
713 via_write_reg_mask(VIASR, 0x16, value, 0x40);
803 via_write_reg_mask(VIASR, 0x1E, value, 0xC0);
821 via_write_reg_mask(VIASR, 0x1E, value, 0x30);
839 via_write_reg_mask(VIASR, 0x2A, value, 0x03);
857 via_write_reg_mask(VIASR, 0x2A, value, 0x0C);
960 viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1);
995 viafb_write_reg_mask(cr_index, VIASR, data, reg_mask);
1024 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
[all...]
H A Dvia-core.c27 [VIA_PORT_26] = { VIA_PORT_I2C, VIA_MODE_I2C, VIASR, 0x26 },
28 [VIA_PORT_31] = { VIA_PORT_I2C, VIA_MODE_I2C, VIASR, 0x31 },
29 [VIA_PORT_25] = { VIA_PORT_GPIO, VIA_MODE_GPIO, VIASR, 0x25 },
30 [VIA_PORT_2C] = { VIA_PORT_GPIO, VIA_MODE_I2C, VIASR, 0x2c },
31 [VIA_PORT_3D] = { VIA_PORT_GPIO, VIA_MODE_GPIO, VIASR, 0x3d },
40 [VIA_PORT_26] = { VIA_PORT_I2C, VIA_MODE_I2C, VIASR, 0x26 },
41 [VIA_PORT_31] = { VIA_PORT_I2C, VIA_MODE_I2C, VIASR, 0x31 },
42 [VIA_PORT_25] = { VIA_PORT_GPIO, VIA_MODE_GPIO, VIASR, 0x25 },
43 [VIA_PORT_2C] = { VIA_PORT_GPIO, VIA_MODE_GPIO, VIASR, 0x2c },
44 [VIA_PORT_3D] = { VIA_PORT_GPIO, VIA_MODE_GPIO, VIASR,
[all...]
H A Dviafbdev.c1114 (viafb_read_reg(VIASR, SR2A) & BIT5) >> 4 |
1115 (viafb_read_reg(VIASR, SR1B) & BIT1) >> 1;
1117 (viafb_read_reg(VIASR, SR2A) & BIT4) >> 3 |
1118 (viafb_read_reg(VIASR, SR1E) & BIT2) >> 2;
1155 viafb_write_reg_mask(SR2A, VIASR,
1157 viafb_write_reg_mask(SR1B, VIASR,
1161 viafb_write_reg_mask(SR2A, VIASR,
1163 viafb_write_reg_mask(SR1E, VIASR,
1188 dvp1_data_dri = (viafb_read_reg(VIASR, SR65) & 0x0c) >> 2;
1189 dvp1_clk_dri = viafb_read_reg(VIASR, SR6
[all...]
H A Dlcd.c704 viafb_write_reg_mask(SR1E, VIASR, 0x00, 0x30);
725 viafb_write_reg_mask(SR3D, VIASR, 0x00, 0x20);
769 viafb_write_reg_mask(SR1E, VIASR, 0x30, 0x30);
791 viafb_write_reg_mask(SR3D, VIASR, 0x20, 0x20);
H A Dvia_modesetting.c187 via_write_reg_mask(VIASR, 0x15, value, 0x1C);
/linux-master/include/linux/
H A Dvia-core.h184 #define VIASR 0x3C4 macro
/linux-master/drivers/media/platform/via/
H A Dvia-camera.c1039 via_write_reg_mask(VIASR, 0x78, 0, 0x80);
1040 via_write_reg_mask(VIASR, 0x1e, 0xc0, 0xc0);
1207 via_write_reg_mask(VIASR, 0x78, 0, 0x80);
1208 via_write_reg_mask(VIASR, 0x1e, 0xc0, 0xc0);

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