Searched refs:VC4_SET_FIELD (Results 1 - 13 of 13) sorted by path

/linux-master/drivers/gpu/drm/vc4/
H A Dvc4_crtc.c279 ret |= VC4_SET_FIELD((level >> 6),
282 return ret | VC4_SET_FIELD(level & 0x3f,
363 VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc,
365 VC4_SET_FIELD((mode->hsync_end - mode->hsync_start) * pixel_rep / ppc,
369 VC4_SET_FIELD((mode->hsync_start - mode->hdisplay) * pixel_rep / ppc,
371 VC4_SET_FIELD(mode->hdisplay * pixel_rep / ppc,
395 VC4_SET_FIELD(vert_bp_even, PV_VERTA_VBP) |
396 VC4_SET_FIELD(vert_sync, PV_VERTA_VSYNC));
398 VC4_SET_FIELD(vert_fp_even, PV_VERTB_VFP) |
399 VC4_SET_FIELD(mod
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H A Dvc4_dpi.c160 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_1, DPI_FORMAT);
170 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB,
174 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB,
176 dpi_c |= VC4_SET_FIELD(DPI_ORDER_BGR,
180 dpi_c |= VC4_SET_FIELD(DPI_ORDER_BGR, DPI_ORDER);
183 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_2,
187 dpi_c |= VC4_SET_FIELD(DPI_ORDER_BGR, DPI_ORDER);
190 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_1,
194 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_16BIT_565_RGB_1,
198 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_16BIT_565_RGB_
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H A Dvc4_dsi.c943 u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) |
944 VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ));
958 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE1) |
959 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE0) |
960 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_CLANE));
962 u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) |
963 VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ) |
964 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_CLANE) |
965 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE0) |
966 VC4_SET_FIELD(
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H A Dvc4_gem.c447 VC4_SET_FIELD(0xf, V3D_SLCACTL_T1CC) |
448 VC4_SET_FIELD(0xf, V3D_SLCACTL_T0CC) |
449 VC4_SET_FIELD(0xf, V3D_SLCACTL_UCC) |
450 VC4_SET_FIELD(0xf, V3D_SLCACTL_ICC));
462 VC4_SET_FIELD(0xf, V3D_SLCACTL_T1CC) |
463 VC4_SET_FIELD(0xf, V3D_SLCACTL_T0CC));
H A Dvc4_hdmi.c1185 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
1201 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
1419 u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
1438 csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD,
1443 csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE,
1446 if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY,
1481 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1483 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1485 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
1486 u32 vertb = (VC4_SET_FIELD(
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H A Dvc4_hdmi_phy.c399 VC4_SET_FIELD(0, VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1_MIN_LIMIT));
404 VC4_SET_FIELD(0, VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2_MAX_LIMIT));
407 VC4_SET_FIELD(phy_get_rm_offset(vco_freq),
412 VC4_SET_FIELD(vco_div, VC4_HDMI_TX_PHY_CLK_DIV_VCO));
415 VC4_SET_FIELD(0xe147, VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4_HOLD_THRESHOLD) |
416 VC4_SET_FIELD(0xe14, VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4_STABLE_THRESHOLD));
422 VC4_SET_FIELD(vco_sel, VC4_HDMI_TX_PHY_PLL_CTL_0_VCO_SEL));
427 VC4_SET_FIELD(3, VC4_HDMI_TX_PHY_PLL_CTL_1_POST_RST_SEL) |
428 VC4_SET_FIELD(1, VC4_HDMI_TX_PHY_PLL_CTL_1_FREQ_DOUBLER_DELAY) |
429 VC4_SET_FIELD(
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H A Dvc4_hvs.c376 dispctrl |= VC4_SET_FIELD(mode->hdisplay,
378 VC4_SET_FIELD(mode->vdisplay,
383 dispctrl |= VC4_SET_FIELD(mode->hdisplay,
385 VC4_SET_FIELD(mode->vdisplay,
901 reg | VC4_SET_FIELD(0, SCALER_DISPECTRL_DSP2_MUX));
906 reg | VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX));
911 reg | VC4_SET_FIELD(3, SCALER_DISPEOLN_DSP4_MUX));
916 reg | VC4_SET_FIELD(3, SCALER_DISPDITHER_DSP5_MUX));
961 dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC0);
962 dispctrl |= VC4_SET_FIELD(
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H A Dvc4_kms.c143 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[0]),
145 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[3]),
147 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[6]),
150 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[1]),
152 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[4]),
154 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[7]),
157 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[2]),
159 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[5]),
161 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[8]),
166 VC4_SET_FIELD(ctm_stat
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H A Dvc4_plane.c534 VC4_SET_FIELD(scale, SCALER_TPZ0_SCALE) |
535 VC4_SET_FIELD(0, SCALER_TPZ0_IPHASE));
537 VC4_SET_FIELD(recip, SCALER_TPZ1_RECIP));
546 VC4_SET_FIELD(scale, SCALER_PPF_SCALE) |
547 VC4_SET_FIELD(0, SCALER_PPF_IPHASE));
772 return VC4_SET_FIELD(SCALER_POS2_ALPHA_MODE_FIXED,
777 return VC4_SET_FIELD(SCALER_POS2_ALPHA_MODE_FIXED,
781 return VC4_SET_FIELD(SCALER_POS2_ALPHA_MODE_PIPELINE,
785 return VC4_SET_FIELD(SCALER_POS2_ALPHA_MODE_PIPELINE,
793 return VC4_SET_FIELD(SCALER5_CTL2_ALPHA_MODE_FIXE
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H A Dvc4_regs.h14 #define VC4_SET_FIELD(value, field) \ macro
H A Dvc4_render_cl.c84 VC4_SET_FIELD(VC4_LOADSTORE_TILE_BUFFER_NONE,
H A Dvc4_txp.c311 VC4_SET_FIELD(0xf, TXP_BYTE_ENABLE) |
312 VC4_SET_FIELD(txp_fmts[i], TXP_FORMAT);
330 VC4_SET_FIELD(mode->hdisplay, TXP_WIDTH) |
331 VC4_SET_FIELD(mode->vdisplay, TXP_HEIGHT));
H A Dvc4_validate.c417 VC4_SET_FIELD(VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_32,
419 VC4_SET_FIELD(VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_128,

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