Searched refs:VC4_GET_FIELD (Results 1 - 8 of 8) sorted by last modified time

/linux-master/drivers/gpu/drm/vc4/
H A Dvc4_regs.h20 #define VC4_GET_FIELD(word, field) FIELD_GET(field##_MASK, word) macro
H A Dvc4_v3d.c106 uint32_t nslc = VC4_GET_FIELD(ident1, V3D_IDENT1_NSLC);
107 uint32_t tups = VC4_GET_FIELD(ident1, V3D_IDENT1_TUPS);
108 uint32_t qups = VC4_GET_FIELD(ident1, V3D_IDENT1_QUPS);
111 VC4_GET_FIELD(ident1, V3D_IDENT1_REV));
116 VC4_GET_FIELD(ident1, V3D_IDENT1_NSEM));
H A Dvc4_hvs.c118 dispstat = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(i)),
137 VC4_GET_FIELD(dlist_word,
271 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT1),
275 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT1),
279 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT2),
429 WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)),
H A Dvc4_dsi.c1302 u32 rxlen = VC4_GET_FIELD(rxpkt1h,
1317 msg_rx[0] = VC4_GET_FIELD(rxpkt1h,
1320 msg_rx[1] = VC4_GET_FIELD(rxpkt1h,
H A Dvc4_crtc.c91 u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
92 u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
133 *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE);
545 encoder_sel = VC4_GET_FIELD(CRTC_READ(PV_CONTROL), PV_CONTROL_CLK_SELECT);
H A Dvc4_kms.c270 VC4_GET_FIELD(HVS_READ(SCALER_DISPCTRL),
H A Dvc4_validate.c587 uint32_t miplevels = VC4_GET_FIELD(p0, VC4_TEX_P0_MIPLVLS);
588 uint32_t width = VC4_GET_FIELD(p1, VC4_TEX_P1_WIDTH);
589 uint32_t height = VC4_GET_FIELD(p1, VC4_TEX_P1_HEIGHT);
621 if (VC4_GET_FIELD(p2, VC4_TEX_P2_PTYPE) ==
624 if (VC4_GET_FIELD(p3, VC4_TEX_P2_PTYPE) ==
639 type = (VC4_GET_FIELD(p0, VC4_TEX_P0_TYPE) |
640 (VC4_GET_FIELD(p1, VC4_TEX_P1_TYPE4) << 4));
H A Dvc4_render_cl.c440 uint8_t tiling = VC4_GET_FIELD(surf->bits,
442 uint8_t buffer = VC4_GET_FIELD(surf->bits,
444 uint8_t format = VC4_GET_FIELD(surf->bits,
539 uint8_t tiling = VC4_GET_FIELD(surf->bits,
541 uint8_t format = VC4_GET_FIELD(surf->bits,

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