Searched refs:V7M_SCB_CTR (Results 1 - 5 of 5) sorted by last modified time

/linux-master/arch/arm/include/asm/
H A Dcachetype.h92 writel(cache_selector, BASEADDR_V7M_SCB + V7M_SCB_CTR);
H A Dcputype.h208 return readl(BASEADDR_V7M_SCB + V7M_SCB_CTR);
H A Dv7m.h58 #define V7M_SCB_CTR 0x7c /* Cache Type register */ macro
/linux-master/arch/arm/mm/
H A Dproc-macros.S76 movw \tmp, #:lower16:BASEADDR_V7M_SCB + V7M_SCB_CTR
77 movt \tmp, #:upper16:BASEADDR_V7M_SCB + V7M_SCB_CTR
94 movw \tmp, #:lower16:BASEADDR_V7M_SCB + V7M_SCB_CTR
95 movt \tmp, #:upper16:BASEADDR_V7M_SCB + V7M_SCB_CTR
/linux-master/arch/arm/boot/compressed/
H A Dhead.S692 movw \tmp, #:lower16:BASEADDR_V7M_SCB + V7M_SCB_CTR
693 movt \tmp, #:upper16:BASEADDR_V7M_SCB + V7M_SCB_CTR

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