Searched refs:TRCVMIDCCTLR1 (Results 1 - 3 of 3) sorted by path

/linux-master/drivers/hwtracing/coresight/
H A Dcoresight-etm4x-cfg.c55 ((offset >= TRCCIDCCTLR0) && (offset <= TRCVMIDCCTLR1))) {
74 CHECKREG(TRCVMIDCCTLR1, vmid_mask1);
H A Dcoresight-etm4x-core.c498 etm4x_relaxed_write32(csa, config->vmid_mask1, TRCVMIDCCTLR1);
1796 state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR1);
1921 etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR1);
H A Dcoresight-etm4x.h96 #define TRCVMIDCCTLR1 0x68C
436 CASE_##op((val), TRCVMIDCCTLR1) \
102 #define TRCVMIDCCTLR1 macro

Completed in 172 milliseconds