#
1bbe0a24 |
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31-Jan-2024 |
Mao Jinlong <quic_jinlmao@quicinc.com> |
coresight: etm4x: Set skip_power_up in etm4_init_arch_data function skip_power_up is used in etm4_init_arch_data when set lpoverride. So need to set the value of it before calling using it. Fixes: 5214b563588e ("coresight: etm4x: Add support for sysreg only devices") Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20240131105423.9519-1-quic_jinlmao@quicinc.com
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#
bcaabb95 |
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29-Jan-2024 |
James Clark <james.clark@arm.com> |
coresight: Add helper for setting csdev->mode Now that mode is in struct coresight_device, sets can be wrapped. This also allows us to add a sanity check that there have been no concurrent modifications of mode. Currently all usages of local_set() were inside the device's spin locks so this new warning shouldn't be triggered. coresight_take_mode() could maybe have been used in place of adding the warning, but there may be use cases which set the mode to the same mode which are valid but would fail in coresight_take_mode() because it requires the device to only be in the disabled state. Signed-off-by: James Clark <james.clark@arm.com> Link: https://lore.kernel.org/r/20240129154050.569566-13-james.clark@arm.com Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
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#
c95c2733 |
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29-Jan-2024 |
James Clark <james.clark@arm.com> |
coresight: Add a helper for getting csdev->mode Now that mode is in struct coresight_device accesses can be wrapped. Signed-off-by: James Clark <james.clark@arm.com> Link: https://lore.kernel.org/r/20240129154050.569566-12-james.clark@arm.com Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
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d724f652 |
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29-Jan-2024 |
James Clark <james.clark@arm.com> |
coresight: Add helper for atomically taking the device Now that mode is in struct coresight_device, this pattern can be wrapped in a helper. Signed-off-by: James Clark <james.clark@arm.com> Link: https://lore.kernel.org/r/20240129154050.569566-11-james.clark@arm.com Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
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#
1f5149c7 |
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29-Jan-2024 |
James Clark <james.clark@arm.com> |
coresight: Move all sysfs code to sysfs file At the moment the core file contains both sysfs functionality and core functionality, while the Perf mode is in a separate file in coresight-etm-perf.c Many of the functions have ambiguous names like coresight_enable_source() which actually only work in relation to the sysfs mode. To avoid further confusion, move everything that isn't core functionality into the sysfs file and append _sysfs to the ambiguous functions. Signed-off-by: James Clark <james.clark@arm.com> Link: https://lore.kernel.org/r/20240129154050.569566-7-james.clark@arm.com Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
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#
9cae77cf |
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29-Jan-2024 |
James Clark <james.clark@arm.com> |
coresight: Move mode to struct coresight_device Most devices use mode, so move the mode definition out of the individual devices and up to the Coresight device. This will allow the core code to also know the mode which will be useful in a later commit. This also fixes the inconsistency of the documentation of the mode field on the individual device types. For example ETB10 had "this ETB is being used". Two devices didn't require an atomic mode type, so these usages have been converted to atomic_get() and atomic_set() only to make it compile, but the documentation of the field in struct coresight_device explains this type of usage. In the future, manipulation of the mode could be completely moved out of the individual devices and into the core code because it's almost all duplicate code, and this change is a step towards that. Signed-off-by: James Clark <james.clark@arm.com> Link: https://lore.kernel.org/r/20240129154050.569566-5-james.clark@arm.com Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
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#
8a519235 |
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22-Nov-2023 |
James Clark <james.clark@arm.com> |
coresight: Fix uninitialized struct warnings These warnings would be hit with the following W=1 build change so initialize all structs properly. Signed-off-by: James Clark <james.clark@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20231123120459.287578-2-james.clark@arm.com
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#
4445e142 |
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16-Nov-2023 |
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> |
coresight: etm4x: Convert to platform remove callback returning void The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is ignored (apart from emitting a warning) and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new(), which already returns void. Eventually after all drivers are converted, .remove_new() will be renamed to .remove(). Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Reviewed-by: James Clark <james.clark@arm.com> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20231116173301.708873-10-u.kleine-koenig@pengutronix.de
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#
94566c5b |
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20-Sep-2023 |
Anshuman Khandual <anshuman.khandual@arm.com> |
coresight: etm: Make cycle count threshold user configurable When cycle counting is enabled, we use a default threshold value i.e 0x100 for the instruction trace cycle counting. This patch makes the cycle threshold user configurable via perf event attributes( 'cc_threshold' => event->attr.config3[11:0] ), falling back to the current default if unspecified. Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: James Clark <james.clark@arm.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-doc@vger.kernel.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Mike Leach <mike.leach@linaro.org> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20230921033631.1298723-3-anshuman.khandual@arm.com
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#
4aff040b |
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20-Sep-2023 |
Anshuman Khandual <anshuman.khandual@arm.com> |
coresight: etm: Override TRCIDR3.CCITMIN on errata affected cpus This work arounds errata 1490853 on Cortex-A76, and Neoverse-N1, errata 1491015 on Cortex-A77, errata 1502854 on Cortex-X1, and errata 1619801 on Neoverse-V1, based affected cpus, where software read for TRCIDR3.CCITMIN field in ETM gets an wrong value. If software uses the value returned by the TRCIDR3.CCITMIN register field, then it will limit the range which could be used for programming the ETM. In reality, the ETM could be programmed with a much smaller value than what is indicated by the TRCIDR3.CCITMIN field and still function correctly. If software reads the TRCIDR3.CCITMIN register field, corresponding to the instruction trace counting minimum threshold, observe the value 0x100 or a minimum cycle count threshold of 256. The correct value should be 0x4 or a minimum cycle count threshold of 4. This work arounds the problem via storing 4 in drvdata->ccitmin on affected systems where the TRCIDR3.CCITMIN has been 256, thus preserving cycle count threshold granularity. These errata information has been updated in Documentation/arch/arm64/silicon-errata.rst, but without their corresponding configs because these have been implemented directly in the driver. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: James Clark <james.clark@arm.com> Cc: Jonathan Corbet <corbet@lwn.net> Cc: linux-doc@vger.kernel.org Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Mike Leach <mike.leach@linaro.org> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> [ Fixed location of silicon-errata.rst in commit description ] Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20230921033631.1298723-2-anshuman.khandual@arm.com
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#
348ddab8 |
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29-Sep-2023 |
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> |
coresight: etm4x: Remove bogous __exit annotation for some functions etm4_platform_driver (which lives in ".data" contains a reference to etm4_remove_platform_dev(). So the latter must not be marked with __exit which results in the function being discarded for a build with CONFIG_CORESIGHT_SOURCE_ETM4X=y which in turn makes the remove pointer contain invalid data. etm4x_amba_driver referencing etm4_remove_amba() has the same issue. Drop the __exit annotations for the two affected functions and a third one that is called by the other two. For reasons I don't understand this isn't catched by building with CONFIG_DEBUG_SECTION_MISMATCH=y. Fixes: c23bc382ef0e ("coresight: etm4x: Refactor probing routine") Fixes: 5214b563588e ("coresight: etm4x: Add support for sysreg only devices") Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Reviewed-by: James Clark <james.clark@arm.com> Link: https://lore.kernel.org/all/20230929081540.yija47lsj35xtj4v@pengutronix.de/ Link: https://lore.kernel.org/r/20230929081637.2377335-1-u.kleine-koenig@pengutronix.de Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
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#
a4621fd1 |
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16-Aug-2023 |
Anshuman Khandual <anshuman.khandual@arm.com> |
coresight: etm4x: Ensure valid drvdata and clock before clk_put() This validates 'drvdata' and 'drvdata->pclk' clock before calling clk_put() in etm4_remove_platform_dev(). The problem was detected using Smatch static checker as reported. Fixes: 73d779a03a76a ("coresight: etm4x: Change etm4_platform_driver driver for MMIO devices") Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: James Clark <james.clark@arm.com> Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reported-by: Dan Carpenter <dan.carpenter@linaro.org> Closes: https://lists.linaro.org/archives/list/coresight@lists.linaro.org/thread/G4N6P4OXELPLLQSNU3GU2MR4LOLRXRMJ/ Reviewed-by: James Clark <james.clark@arm.com> Reviewed-by: Mike Leach <mike.leach@lnaro.org> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20230817035926.157370-1-anshuman.khandual@arm.com
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#
134124ac |
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10-Jul-2023 |
Suzuki K Poulose <suzuki.poulose@arm.com> |
coresight: etm4x: Add ACPI support in platform driver Drop ETM4X ACPI ID from the AMBA ACPI device list, and instead just move it inside the new ACPI devices list detected and used via platform driver. Cc: "Rafael J. Wysocki" <rafael@kernel.org> Cc: Len Brown <lenb@kernel.org> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Leo Yan <leo.yan@linaro.org> Cc: Sudeep Holla <sudeep.holla@arm.com> Cc: Lorenzo Pieralisi <lpieralisi@kernel.org> Cc: linux-acpi@vger.kernel.org Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> (for ACPI specific changes) Acked-by: "Rafael J. Wysocki" <rafael@kernel.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Tested-by: Tanmay Jagdale <tanmay@marvell.com> Link: https://lore.kernel.org/r/20230710062500.45147-7-anshuman.khandual@arm.com
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#
73d779a0 |
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10-Jul-2023 |
Anshuman Khandual <anshuman.khandual@arm.com> |
coresight: etm4x: Change etm4_platform_driver driver for MMIO devices Add support for handling MMIO based devices via platform driver. We need to make sure that : 1) The APB clock, if present is enabled at probe and via runtime_pm ops 2) Use the ETM4x architecture or CoreSight architecture registers to identify a device as CoreSight ETM4x, instead of relying a white list of "Peripheral IDs" The driver doesn't get to handle the devices yet, until we wire the ACPI changes to move the devices to be handled via platform driver than the etm4_amba driver. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Leo Yan <leo.yan@linaro.org> Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Acked-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20230710062500.45147-5-anshuman.khandual@arm.com
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#
5a1c7097 |
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10-Jul-2023 |
Anshuman Khandual <anshuman.khandual@arm.com> |
coresight: etm4x: Drop pid argument from etm4_probe() Coresight device pid can be retrieved from its iomem base address, which is stored in 'struct etm4x_drvdata'. This drops pid argument from etm4_probe() and 'struct etm4_init_arg'. Instead etm4_check_arch_features() derives the coresight device pid with a new helper coresight_get_pid(), right before it is consumed in etm4_hisi_match_pid(). Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Leo Yan <leo.yan@linaro.org> Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20230710062500.45147-4-anshuman.khandual@arm.com
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#
4e3b9a6e |
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10-Jul-2023 |
Anshuman Khandual <anshuman.khandual@arm.com> |
coresight: etm4x: Drop iomem 'base' argument from etm4_probe() 'struct etm4_drvdata' itself can carry the base address before etm4_probe() gets called. Just drop that redundant argument from etm4_probe(). Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Leo Yan <leo.yan@linaro.org> Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: James Clark <james.clark@arm.com> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20230710062500.45147-3-anshuman.khandual@arm.com
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#
3095e90e |
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10-Jul-2023 |
Anshuman Khandual <anshuman.khandual@arm.com> |
coresight: etm4x: Allocate and device assign 'struct etmv4_drvdata' earlier Allocate and device assign 'struct etmv4_drvdata' earlier during the driver probe, ensuring that it can be retrieved in power management based runtime callbacks if required. This will also help in dropping iomem base address argument from the function etm4_probe() later. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Leo Yan <leo.yan@linaro.org> Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20230710062500.45147-2-anshuman.khandual@arm.com
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#
ab5ca626 |
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05-Jun-2023 |
Suzuki K Poulose <suzuki.poulose@arm.com> |
coresight: etm4x: Match all ETM4 instances based on DEVARCH and DEVTYPE Instead of adding the PIDs forever to the list for the new CPUs, let us detect a component to be ETMv4 based on the CoreSight CID, DEVTYPE=PE_TRACE and DEVARCH=ETMv4. This is already done for some of the ETMs. We can extend the PID matching to match the PIDR2:JEDEC, BIT[3], which must be 1 (RAO) always. Link: https://lkml.kernel.org/r/20230317030501.1811905-1-anshuman.khandual@arm.com Cc: Anshuman Khandual <anshuman.khandual@arm.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: frowand.list@gmail.com Cc: linux@armlinux.org.uk Cc: Mike Leach <mike.leach@linaro.org> Reviewed-by: Mike Leach <mike.leach@linaro.org> [ Fixed typo in the description RA0 => RAO ] Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20230605133031.1827626-1-suzuki.poulose@arm.com
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#
c5f231f1 |
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18-May-2023 |
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> |
coresight: etm4x: Make etm4_remove_dev() return void etm4_remove_dev() returned zero unconditionally. Make it return void instead, which makes it clear in the callers that there is no error to handle. Simplify etm4_remove_platform_dev() accordingly. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20230518201629.260672-1-u.kleine-koenig@pengutronix.de
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9fa36828 |
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25-Apr-2023 |
James Clark <james.clark@arm.com> |
coresight: Use enum type for cs_mode wherever possible mode is stored as a local_t, but it is also passed around a lot as a plain u32, so use the correct type wherever local_t isn't currently used. This helps a little bit with readability. Reviewed-by: Mike Leach <mike.leach@linaro.org> Signed-off-by: James Clark <james.clark@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20230425143542.2305069-3-james.clark@arm.com
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735e7b30 |
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21-Mar-2023 |
Suzuki K Poulose <suzuki.poulose@arm.com> |
coresight: etm4x: Do not access TRCIDR1 for identification CoreSight ETM4x architecture clearly provides ways to identify a device via registers in the "Management" class, TRCDEVARCH and TRCDEVTYPE. These registers can be accessed without the Trace domain being powered on. We additionally added TRCIDR1 as fallback in order to cover for any ETMs that may not have implemented TRCDEVARCH. So far, nobody has reported hitting a WARNING we placed to catch such systems. Also, more importantly it is problematic to access TRCIDR1, which is a "Trace" register via MMIO access, without clearing the OSLK. But we cannot mess with the OSLK until we know for sure that this is an ETMv4 device. Thus, this kind of creates a chicken and egg problem unnecessarily for systems "which are compliant" to the ETMv4 architecture. Let us remove the TRCIDR1 fall back check and rely only on TRCDEVARCH. Fixes: 8b94db1edaee ("coresight: etm4x: Use TRCDEVARCH for component discovery") Cc: stable@vger.kernel.org Reported-by: Steve Clevenger <scclevenger@os.amperecomputing.com> Link: https://lore.kernel.org/all/143540e5623d4c7393d24833f2b80600d8d745d2.1677881753.git.scclevenger@os.amperecomputing.com/ Cc: Mike Leach <mike.leach@linaro.org> Cc: James Clark <james.clark@arm.com> Reviewed-by: Mike Leach <mike.leach@linaro.org> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20230321104530.1547136-1-suzuki.poulose@arm.com
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#
bf84937e |
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27-Feb-2023 |
Steve Clevenger <scclevenger@os.amperecomputing.com> |
coresight-etm4: Fix for() loop drvdata->nr_addr_cmp range bug In etm4_enable_hw, fix for() loop range to represent address comparator pairs. Fixes: 2e1cdfe184b5 ("coresight-etm4x: Adding CoreSight ETM4x driver") Cc: stable@vger.kernel.org Signed-off-by: Steve Clevenger <scclevenger@os.amperecomputing.com> Reviewed-by: James Clark <james.clark@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/4a4ee61ce8ef402615a4528b21a051de3444fb7b.1677540079.git.scclevenger@os.amperecomputing.com
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#
42708bac |
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15-Jan-2023 |
Mike Leach <mike.leach@linaro.org> |
coresight: etmX.X: stm: Remove trace_id() callback CoreSight sources provide a callback (.trace_id) in the standard source ops which returns the ID to the core code. This was used to check that sources all had a unique Trace ID. Uniqueness is now gauranteed by the Trace ID allocation system, and the check code has been removed from the core. This patch removes the unneeded and unused .trace_id source ops from the ops structure and implementations in etm3x, etm4x and stm. Signed-off-by: Mike Leach <mike.leach@linaro.org> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20230116124928.5440-8-mike.leach@linaro.org
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#
df487120 |
|
15-Jan-2023 |
Mike Leach <mike.leach@linaro.org> |
coresight: etm4x: Update ETM4 driver to use Trace ID API The trace ID API is now used to allocate trace IDs for ETM4.x / ETE devices. For perf sessions, these will be allocated on enable, and released on disable. For sysfs sessions, these will be allocated on enable, but only released on reset. This allows the sysfs session to interrogate the Trace ID used after the session is over - maintaining functional consistency with the previous allocation scheme. The trace ID will also be allocated on read of the mgmt/trctraceid file. This ensures that if perf or sysfs read this before enabling trace, the value will be the one used for the trace session. Trace ID initialisation is removed from the _probe() function. Signed-off-by: Mike Leach <mike.leach@linaro.org> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20230116124928.5440-6-mike.leach@linaro.org
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#
589d9282 |
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14-Jan-2023 |
Junhao He <hejunhao3@huawei.com> |
coresight: etm4x: Fix accesses to TRCSEQRSTEVR and TRCSEQSTR The TRCSEQRSTEVR and TRCSEQSTR registers are not implemented if the TRCIDR5.NUMSEQSTATE == 0. Skip accessing the registers in such cases. Fixes: 2e1cdfe184b5 ("coresight-etm4x: Adding CoreSight ETM4x driver") Signed-off-by: Junhao He <hejunhao3@huawei.com> Reviewed-by: Mike Leach <mike.leach@linaro.org> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20230114091632.60095-1-hejunhao3@huawei.com
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#
c767c347 |
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19-Oct-2022 |
Jilin Yuan <yuanjilin@cdjrlc.com> |
coresight: etm4x: fix repeated words in comments Delete the redundant word 'the'. Signed-off-by: Jilin Yuan <yuanjilin@cdjrlc.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20221019124953.45885-1-yuanjilin@cdjrlc.com
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3c728e07 |
|
05-Jul-2022 |
Tamas Zsoldos <tamas.zsoldos@arm.com> |
coresight: etm4x: add CPU hotplug support for probing etm4x devices cannot be successfully probed when their CPU is offline. For example, when booting with maxcpus=n, ETM probing will fail on CPUs >n, and the probing won't be reattempted once the CPUs come online. This will leave those CPUs unable to make use of ETM. This change adds a mechanism to delay the probing if the corresponding CPU is offline, and to try it again when the CPU comes online. Signed-off-by: Tamas Zsoldos <tamas.zsoldos@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20220705145935.24679-1-tamas.zsoldos@arm.com
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#
db74cd63 |
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19-Sep-2022 |
Nathan Chancellor <nathan@kernel.org> |
arm64/sysreg: Fix a few missed conversions After the conversion to automatically generating the ID_AA64DFR0_EL1 definition names, the build fails in a few different places because some of the definitions were not changed to their new names along the way. Update the names to resolve the build errors. Fixes: c0357a73fa4a ("arm64/sysreg: Align field names in ID_AA64DFR0_EL1 with architecture") Signed-off-by: Nathan Chancellor <nathan@kernel.org> Reviewed-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220919160928.3905780-1-nathan@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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#
018b741e |
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18-May-2022 |
Sai Prakash Ranjan <quic_saipraka@quicinc.com> |
coresight: etm4x: Use asm-generic IO memory barriers Per discussion in [1], it was decided to move to using architecture independent/asm-generic IO memory barriers to have just one set of them and deprecate use of arm64 specific IO memory barriers in driver code. So replace current usage of __io_rmb()/__iowmb() in drivers to __io_ar()/__io_bw(). [1] https://lore.kernel.org/lkml/CAK8P3a0L2tLeF1Q0+0ijUxhGNaw+Z0fyPC1oW6_ELQfn0=i4iw@mail.gmail.com/ Signed-off-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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#
2d693ed4 |
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11-May-2022 |
James Clark <james.clark@arm.com> |
coresight: Add config flag to enable branch broadcast When enabled, all taken branch addresses are output, even if the branch was because of a direct branch instruction. This enables reconstruction of the program flow without having access to the memory image of the code being executed. Use bit 8 for the config option which would be the correct bit for programming ETMv3. Although branch broadcast can't be enabled on ETMv3 because it's not in the define ETM3X_SUPPORTED_OPTIONS, using the correct bit might help prevent future collisions or allow it to be enabled if needed. Signed-off-by: James Clark <james.clark@arm.com> Reviewed-by: Mike Leach <mike.leach@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20220511144601.2257870-2-james.clark@arm.com
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#
0544f32b |
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04-Mar-2022 |
James Clark <james.clark@arm.com> |
coresight: etm4x: Cleanup TRCSSCCRn and TRCSSCSRn register accesses This is a no-op change for style and consistency and has no effect on the binary output by the compiler. In sysreg.h fields are defined as the register name followed by the field name and then _MASK. This allows for grepping for fields by name rather than using magic numbers. Signed-off-by: James Clark <james.clark@arm.com> Reviewed-by: Mike Leach <mike.leach@linaro.org> Link: https://lore.kernel.org/r/20220304171913.2292458-13-james.clark@arm.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
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#
6ba7f2bc |
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04-Mar-2022 |
James Clark <james.clark@arm.com> |
coresight: etm4x: Cleanup TRCVICTLR register accesses This is a no-op change for style and consistency and has no effect on the binary output by the compiler. In sysreg.h fields are defined as the register name followed by the field name and then _MASK. This allows for grepping for fields by name rather than using magic numbers. Signed-off-by: James Clark <james.clark@arm.com> Reviewed-by: Mike Leach <mike.leach@linaro.org> Link: https://lore.kernel.org/r/20220304171913.2292458-10-james.clark@arm.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
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#
1cf50f64 |
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04-Mar-2022 |
James Clark <james.clark@arm.com> |
coresight: etm4x: Cleanup TRCCONFIGR register accesses This is a no-op change for style and consistency and has no effect on the binary output by the compiler. In sysreg.h fields are defined as the register name followed by the field name and then _MASK. This allows for grepping for fields by name rather than using magic numbers. Signed-off-by: James Clark <james.clark@arm.com> Reviewed-by: Mike Leach <mike.leach@linaro.org> Link: https://lore.kernel.org/r/20220304171913.2292458-7-james.clark@arm.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
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#
028e5460 |
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04-Mar-2022 |
James Clark <james.clark@arm.com> |
coresight: etm4x: Cleanup TRCIDR5 register accesses This is a no-op change for style and consistency and has no effect on the binary output by the compiler. In sysreg.h fields are defined as the register name followed by the field name and then _MASK. This allows for grepping for fields by name rather than using magic numbers. Signed-off-by: James Clark <james.clark@arm.com> Reviewed-by: Mike Leach <mike.leach@linaro.org> Link: https://lore.kernel.org/r/20220304171913.2292458-6-james.clark@arm.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
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#
ea69dbb8 |
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04-Mar-2022 |
James Clark <james.clark@arm.com> |
coresight: etm4x: Cleanup TRCIDR4 register accesses This is a no-op change for style and consistency and has no effect on the binary output by the compiler. In sysreg.h fields are defined as the register name followed by the field name and then _MASK. This allows for grepping for fields by name rather than using magic numbers. Signed-off-by: James Clark <james.clark@arm.com> Reviewed-by: Mike Leach <mike.leach@linaro.org> Link: https://lore.kernel.org/r/20220304171913.2292458-5-james.clark@arm.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
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#
f4d1f214 |
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04-Mar-2022 |
James Clark <james.clark@arm.com> |
coresight: etm4x: Cleanup TRCIDR3 register accesses This is a no-op change for style and consistency and has no effect on the binary output by the compiler. In sysreg.h fields are defined as the register name followed by the field name and then _MASK. This allows for grepping for fields by name rather than using magic numbers. Signed-off-by: James Clark <james.clark@arm.com> Reviewed-by: Mike Leach <mike.leach@linaro.org> Link: https://lore.kernel.org/r/20220304171913.2292458-4-james.clark@arm.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
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#
cf0c7f18 |
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04-Mar-2022 |
James Clark <james.clark@arm.com> |
coresight: etm4x: Cleanup TRCIDR2 register accesses This is a no-op change for style and consistency and has no effect on the binary output by the compiler. In sysreg.h fields are defined as the register name followed by the field name and then _MASK. This allows for grepping for fields by name rather than using magic numbers. Signed-off-by: James Clark <james.clark@arm.com> Reviewed-by: Mike Leach <mike.leach@linaro.org> Link: https://lore.kernel.org/r/20220304171913.2292458-3-james.clark@arm.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
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#
e601cc9a |
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04-Mar-2022 |
James Clark <james.clark@arm.com> |
coresight: etm4x: Cleanup TRCIDR0 register accesses This is a no-op change for style and consistency and has no effect on the binary output by the compiler. In sysreg.h fields are defined as the register name followed by the field name and then _MASK. This allows for grepping for fields by name rather than using magic numbers. Signed-off-by: James Clark <james.clark@arm.com> Reviewed-by: Mike Leach <mike.leach@linaro.org> Link: https://lore.kernel.org/r/20220304171913.2292458-2-james.clark@arm.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
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#
aab47386 |
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04-Feb-2022 |
Leo Yan <leo.yan@linaro.org> |
coresight: etm4x: Don't trace PID for non-root PID namespace When runs in perf mode, the driver always enables the PID tracing. This can lead confusion when the profiling session runs in non-root PID namespace, whereas it records the PIDs from the root PID namespace. To avoid confusion for PID tracing, when runs in perf mode, this patch changes to only enable PID tracing for root PID namespace. As result, after apply this patch, the perf tool reports PID as '-1' for all samples: # unshare --fork --pid perf record -e cs_etm// -m 64K,64K -a \ -o perf_test.data -- uname # perf report -i perf_test.data --itrace=Zi1000i --stdio # Total Lost Samples: 0 # # Samples: 94 of event 'instructions' # Event count (approx.): 94000 # # Overhead Command Shared Object Symbol # ........ ....... ................. .............................. # 68.09% :-1 [kernel.kallsyms] [k] __sched_text_end 3.19% :-1 [kernel.kallsyms] [k] hrtimer_interrupt 2.13% :-1 [kernel.kallsyms] [k] __bitmap_and 2.13% :-1 [kernel.kallsyms] [k] trace_vbprintk 1.06% :-1 [kernel.kallsyms] [k] __fget_files 1.06% :-1 [kernel.kallsyms] [k] __schedule 1.06% :-1 [kernel.kallsyms] [k] __softirqentry_text_start 1.06% :-1 [kernel.kallsyms] [k] __update_load_avg_cfs_rq 1.06% :-1 [kernel.kallsyms] [k] __update_load_avg_se 1.06% :-1 [kernel.kallsyms] [k] arch_counter_get_cntpct 1.06% :-1 [kernel.kallsyms] [k] check_and_switch_context 1.06% :-1 [kernel.kallsyms] [k] format_decode 1.06% :-1 [kernel.kallsyms] [k] handle_percpu_devid_irq 1.06% :-1 [kernel.kallsyms] [k] irq_enter_rcu 1.06% :-1 [kernel.kallsyms] [k] irqtime_account_irq 1.06% :-1 [kernel.kallsyms] [k] ktime_get 1.06% :-1 [kernel.kallsyms] [k] ktime_get_coarse_real_ts64 1.06% :-1 [kernel.kallsyms] [k] memmove 1.06% :-1 [kernel.kallsyms] [k] perf_ioctl 1.06% :-1 [kernel.kallsyms] [k] perf_output_begin 1.06% :-1 [kernel.kallsyms] [k] perf_output_copy 1.06% :-1 [kernel.kallsyms] [k] profile_tick 1.06% :-1 [kernel.kallsyms] [k] sched_clock 1.06% :-1 [kernel.kallsyms] [k] timerqueue_add 1.06% :-1 [kernel.kallsyms] [k] trace_save_cmdline 1.06% :-1 [kernel.kallsyms] [k] update_load_avg 1.06% :-1 [kernel.kallsyms] [k] vbin_printf Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20220204152403.71775-4-leo.yan@linaro.org
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#
d05bbad0 |
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03-Feb-2022 |
James Clark <james.clark@arm.com> |
coresight: no-op refactor to make INSTP0 check more idiomatic The spec says this: P0 tracing support field. The permitted values are: 0b00 Tracing of load and store instructions as P0 elements is not supported. 0b11 Tracing of load and store instructions as P0 elements is supported, so TRCCONFIGR.INSTP0 is supported. All other values are reserved. The value we are looking for is 0b11 so simplify this. The double read and && was a bit obfuscated. Suggested-by: Suzuki Poulose <suzuki.poulose@arm.com> Signed-off-by: James Clark <james.clark@arm.com> Link: https://lore.kernel.org/r/20220203115336.119735-2-james.clark@arm.com Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
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#
7ebd0ec6 |
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24-Nov-2021 |
Mike Leach <mike.leach@linaro.org> |
coresight: configfs: Allow configfs to activate configuration Adds configfs attributes to allow a configuration to be enabled for use when sysfs is used to control CoreSight. perf retains independent enabling of configurations. Signed-off-by: Mike Leach <mike.leach@linaro.org> Link: https://lore.kernel.org/r/20211124200038.28662-6-mike.leach@linaro.org Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
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#
0605b89d |
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24-Sep-2021 |
Tao Zhang <quic_taozha@quicinc.com> |
coresight: etm4x: Add ETM PID for Kryo-5XX Add ETM PID for Kryo-5XX to the list of supported ETMs. Otherwise, Kryo-5XX ETMs will not be initialized successfully. e.g. This change can be verified on qrb5165-rb5 board. ETM4-ETM7 nodes will not be visible without this change. Signed-off-by: Tao Zhang <quic_taozha@quicinc.com> Link: https://lore.kernel.org/r/1632477981-13632-2-git-send-email-quic_taozha@quicinc.com Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
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#
5f6fd1aa |
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14-Sep-2021 |
Suzuki K Poulose <suzuki.poulose@arm.com> |
coresight: etm4x: Use Trace Filtering controls dynamically The Trace Filtering support (FEAT_TRF) ensures that the ETM can be prohibited from generating any trace for a given EL. This is much stricter knob, than the TRCVICTLR exception level masks, which doesn't prevent the ETM from generating Context packets for an "excluded" EL. At the moment, we do a onetime enable trace at user and kernel and leave it untouched for the kernel life time. This implies that the ETM could potentially generate trace packets containing the kernel addresses, and thus leaking the kernel virtual address in the trace. This patch makes the switch dynamic, by honoring the filters set by the user and enforcing them in the TRFCR controls. We also rename the cpu_enable_tracing() appropriately to cpu_detect_trace_filtering() and the drvdata member trfc => trfcr to indicate the "value" of the TRFCR_EL1. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Al Grant <al.grant@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Leo Yan <leo.yan@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Link: https://lore.kernel.org/r/20210914102641.1852544-3-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
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#
937d3f58 |
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14-Sep-2021 |
Suzuki K Poulose <suzuki.poulose@arm.com> |
coresight: etm4x: Save restore TRFCR_EL1 When the CPU enters a low power mode, the TRFCR_EL1 contents could be reset. Thus we need to save/restore the TRFCR_EL1 along with the ETM4x registers to allow the tracing. The TRFCR related helpers are in a new header file, as we need to use them for TRBE in the later patches. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Anshuman Khandual <anshuman.khandual@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Leo Yan <leo.yan@linaro.org> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20210914102641.1852544-2-suzuki.poulose@arm.com [Fixed cosmetic details] Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
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#
810ac401 |
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18-Aug-2021 |
Mike Leach <mike.leach@linaro.org> |
coresight: etm4x: Add complex configuration handlers to etmv4 Adds in handlers to allow the ETMv4 to use the complex configuration support. Features and configurations can be loaded and selected in the device. Link: https://lore.kernel.org/r/20210723165444.1048-8-mike.leach@linaro.org Signed-off-by: Mike Leach <mike.leach@linaro.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210818194022.379573-8-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
af36b685 |
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14-Jun-2021 |
Junhao He <hejunhao2@hisilicon.com> |
coresight: etm4x: core: Remove redundant check of attr "attr" is checked by perf framework, so remove the redundant check in etm4_parse_event_config(). Link: https://lore.kernel.org/r/1620912469-52222-4-git-send-email-liuqi115@huawei.com Signed-off-by: Junhao He <hejunhao2@hisilicon.com> Signed-off-by: Qi Liu <liuqi115@huawei.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210614175901.532683-5-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
35e1c916 |
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05-Apr-2021 |
Suzuki K Poulose <suzuki.poulose@arm.com> |
coresight: ete: Add support for ETE tracing Add ETE as one of the supported device types we support with ETM4x driver. The devices are named following the existing convention as ete<N>. ETE mandates that the trace resource status register is programmed before the tracing is turned on. For the moment simply write to it indicating TraceActive. Cc: Mike Leach <mike.leach@linaro.org> Reviewed-by: Mike Leach <mike.leach@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20210405164307.1720226-14-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
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#
3e666ad0 |
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05-Apr-2021 |
Suzuki K Poulose <suzuki.poulose@arm.com> |
coresight: ete: Add support for ETE sysreg access Add support for handling the system registers for Embedded Trace Extensions (ETE). ETE shares most of the registers with ETMv4 except for some and also adds some new registers. Re-arrange the ETMv4x list to share the common definitions and add the ETE sysreg support. Cc: Mike Leach <mike.leach@linaro.org> Reviewed-by: Mike Leach <mike.leach@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20210405164307.1720226-13-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
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#
bc2c689f |
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05-Apr-2021 |
Suzuki K Poulose <suzuki.poulose@arm.com> |
coresight: etm4x: Add support for PE OS lock ETE may not implement the OS lock and instead could rely on the PE OS Lock for the trace unit access. This is indicated by the TRCOLSR.OSM == 0b100. Add support for handling the PE OS lock Cc: Mike Leach <mike.leach@linaro.org> Reviewed-by: mike.leach <mike.leach@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20210405164307.1720226-12-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
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#
8b481196 |
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05-Apr-2021 |
Suzuki K Poulose <suzuki.poulose@arm.com> |
coresight: etm4x: Move ETM to prohibited region for disable If the CPU implements Arm v8.4 Trace filter controls (FEAT_TRF), move the ETM to trace prohibited region using TRFCR, while disabling. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Cc: Anshuman Khandual <anshuman.khandual@arm.com> Reviewed-by: Mike Leach <mike.leach@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20210405164307.1720226-9-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
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#
ec585949 |
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07-Apr-2021 |
Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> |
coresight: etm4x: Add ETM PID for Cortex-A78 Add ETM PID for Cortex-A78 to the list of supported ETMs. Link: https://lore.kernel.org/r/20210213112829.26834-1-saiprakash.ranjan@codeaurora.org Reviewed-by: Mike Leach <mike.leach@linaro.org> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20210407160007.418053-2-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
88f11864 |
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11-Feb-2021 |
Suzuki K Poulose <suzuki.poulose@arm.com> |
coresight: etm-perf: Support PID tracing for kernel at EL2 When the kernel is running at EL2, the PID is stored in CONTEXTIDR_EL2. So, tracing CONTEXTIDR_EL1 doesn't give us the pid of the process. Thus we should trace the VMID with VMIDOPT set to trace CONTEXTIDR_EL2 instead of CONTEXTIDR_EL1. Given that we have an existing config option "contextid" and this will be useful for tracing virtual machines (when we get to support virtualization). So instead, this patch extends option CTXTID with an extra bit ETM_OPT_CTXTID2 (bit 15), thus on an EL2 kernel, we will have another bit available for the perf tool: ETM_OPT_CTXTID is for kernel running in EL1, ETM_OPT_CTXTID2 is used when kernel runs in EL2 with VHE enabled. The tool must be backward compatible for users, i.e, "contextid" today traces PID and that should remain the same; for this purpose, the perf tool is updated to automatically set corresponding bit for the "contextid" config, therefore, the user doesn't have to bother which EL the kernel is running. i.e, perf record -e cs_etm/contextid/u -- will always do the "pid" tracing, independent of the kernel EL. The driver parses the format "contextid", which traces CONTEXTIDR_EL1 for ETM_OPT_CTXTID (on EL1 kernel) and traces CONTEXTIDR_EL2 for ETM_OPT_CTXTID2 (on EL2 kernel). Besides the enhancement for format "contexid", extra two formats are introduced: "contextid1" and "contextid2". This considers to support tracing both CONTEXTIDR_EL1 and CONTEXTIDR_EL2 when the kernel is running at EL2. Finally, the PMU formats are defined as follow: "contextid1": Available on both EL1 kernel and EL2 kernel. When the kernel is running at EL1, "contextid1" enables the PID tracing; when the kernel is running at EL2, this enables tracing the PID of guest applications. "contextid2": Only usable when the kernel is running at EL2. When selected, enables PID tracing on EL2 kernel. "contextid": Will be an alias for the option that enables PID tracing. I.e, contextid == contextid1, on EL1 kernel. contextid == contextid2, on EL2 kernel. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Al Grant <al.grant@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Leo Yan <leo.yan@linaro.org> Reviewed-by: Mike Leach <mike.leach@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> [ Added two config formats: contextid1, contextid2 ] Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210206150833.42120-4-leo.yan@linaro.org Link: https://lore.kernel.org/r/20210211172038.2483517-3-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
1609faa9 |
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05-Feb-2021 |
Uwe Kleine-König <uwe@kleine-koenig.org> |
coresight: etm4x: Fix merge resolution for amba rework This was non-trivial to get right because commits c23bc382ef0e ("coresight: etm4x: Refactor probing routine") and 5214b563588e ("coresight: etm4x: Add support for sysreg only devices") changed the code flow considerably. With this change the driver can be built again. Fixes: 0573d3fa4864 ("Merge branch 'devel-stable' of git://git.armlinux.org.uk/~rmk/linux-arm into char-misc-next") Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org> Link: https://lore.kernel.org/r/20210205130848.20009-1-uwe@kleine-koenig.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
f7289606 |
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01-Feb-2021 |
Suzuki K Poulose <suzuki.poulose@arm.com> |
coresight: etm4x: Handle accesses to TRCSTALLCTLR TRCSTALLCTLR register is only implemented if TRCIDR3.STALLCTL == 0b1 Make sure the driver touches the register only it is implemented. Link: https://lore.kernel.org/r/20210127184617.3684379-1-suzuki.poulose@arm.com Cc: stable@vger.kernel.org Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Cc: Leo Yan <leo.yan@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210201181351.1475223-32-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
e5d51fbe |
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01-Feb-2021 |
Jonathan Zhou <jonathan.zhouwen@huawei.com> |
coresight: Add support for v8.4 SelfHosted tracing v8.4 tracing extensions added support for trace filtering controlled by TRFCR_ELx. This must be programmed to allow tracing at EL1/EL2 and EL0. The timestamp used is the virtual time. Also enable CONTEXIDR_EL2 tracing if we are running the kernel at EL2. Link: https://lore.kernel.org/r/20210110224850.1880240-29-suzuki.poulose@arm.com Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Will Deacon <will@kernel.org> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Jonathan Zhou <jonathan.zhouwen@huawei.com> [ Move the trace filtering setup etm_init_arch_data() and clean ups] Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210201181351.1475223-31-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
5214b563 |
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01-Feb-2021 |
Suzuki K Poulose <suzuki.poulose@arm.com> |
coresight: etm4x: Add support for sysreg only devices Add support for devices with system instruction access only. They don't have a memory mapped interface and thus are not AMBA devices. System register access is not permitted to TRCPDCR and thus skip access to them. Link: https://lore.kernel.org/r/20210110224850.1880240-26-suzuki.poulose@arm.com Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210201181351.1475223-28-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
e97db2cf |
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01-Feb-2021 |
Suzuki K Poulose <suzuki.poulose@arm.com> |
coresight: etm4x: Run arch feature detection on the CPU As we are about to add support for system register based devices, we don't get an AMBA pid. So, the detection code could check the system registers running on the CPU to check for the architecture specific features. Thus we move the arch feature detection to run on the CPU. We cannot always read the PID from the HW, as the PID could be overridden by DT for broken devices. So, use the PID from AMBA layer if available. Link: https://lore.kernel.org/r/20210110224850.1880240-25-suzuki.poulose@arm.com Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Cc: liuqi115@huawei.com Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210201181351.1475223-27-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
c23bc382 |
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01-Feb-2021 |
Suzuki K Poulose <suzuki.poulose@arm.com> |
coresight: etm4x: Refactor probing routine CoreSight ETM with system register access may not have a memory mapped i/o access. Refactor the ETM specific probing into a common routine to allow reusing the code for such ETMs. Link: https://lore.kernel.org/r/20210110224850.1880240-24-suzuki.poulose@arm.com Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210201181351.1475223-26-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
dc1747a7 |
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01-Feb-2021 |
Suzuki K Poulose <suzuki.poulose@arm.com> |
coresight: etm4x: Detect system instructions support ETM v4.4 onwards adds support for system instruction access to the ETM. Detect the support on an ETM and switch to using the mode when available. Link: https://lore.kernel.org/r/20210110224850.1880240-23-suzuki.poulose@arm.com Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210201181351.1475223-25-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
1ab3bb9d |
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01-Feb-2021 |
Suzuki K Poulose <suzuki.poulose@arm.com> |
coresight: etm4x: Add necessary synchronization for sysreg access As per the specification any update to the TRCPRGCTLR must be synchronized by a context synchronization event (in our case an explicist ISB) before the TRCSTATR is checked. Link: https://lore.kernel.org/r/20210110224850.1880240-22-suzuki.poulose@arm.com Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210201181351.1475223-24-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
8b94db1e |
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01-Feb-2021 |
Suzuki K Poulose <suzuki.poulose@arm.com> |
coresight: etm4x: Use TRCDEVARCH for component discovery We have been using TRCIDR1 for detecting the ETM version. This is in preparation for the future IP support. Link: https://lore.kernel.org/r/20210110224850.1880240-20-suzuki.poulose@arm.com Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210201181351.1475223-22-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
fd6e7905 |
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01-Feb-2021 |
Suzuki K Poulose <suzuki.poulose@arm.com> |
coresight: etm4x: Detect access early on the target CPU In preparation to detect the support for system instruction support, move the detection of the device access to the target CPU. Link: https://lore.kernel.org/r/20210110224850.1880240-19-suzuki.poulose@arm.com Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210201181351.1475223-21-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
e49516e2 |
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01-Feb-2021 |
Suzuki K Poulose <suzuki.poulose@arm.com> |
coresight: etm4x: Handle ETM architecture version We are about to rely on TRCDEVARCH for detecting the ETM and its architecture version, falling back to TRCIDR1 if the former is not implemented (in older broken implementations). Also, we use the architecture version information to make some decisions. Streamline the architecture version handling by adding helpers. Link: https://lore.kernel.org/r/20210110224850.1880240-18-suzuki.poulose@arm.com Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210201181351.1475223-20-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
4d1b1fd7 |
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01-Feb-2021 |
Suzuki K Poulose <suzuki.poulose@arm.com> |
coresight: etm4x: Clean up exception level masks etm4_get_access_type() calculates the exception level bits for use in address comparator registers. This is also used by the TRCVICTLR register by shifting to the required position. This patch cleans up the logic to make etm4_get_access_type() calculate a generic mask which can be used by all users by shifting to their field. No functional changes intended. Link: https://lore.kernel.org/r/20210110224850.1880240-17-suzuki.poulose@arm.com Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210201181351.1475223-19-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
1d3eead7 |
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01-Feb-2021 |
Suzuki K Poulose <suzuki.poulose@arm.com> |
coresight: etm4x: Cleanup secure exception level masks We rely on the ETM architecture version to decide whether Secure EL2 is available on the CPU for excluding the level for address comparators and viewinst main control register. We must instead use the TRCDIDR3.EXLEVEL_S field to detect the supported levels. Link: https://lore.kernel.org/r/20210110224850.1880240-16-suzuki.poulose@arm.com Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210201181351.1475223-18-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
33d5573a |
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01-Feb-2021 |
Suzuki K Poulose <suzuki.poulose@arm.com> |
coresight: etm4x: Check for Software Lock The Software lock is not implemented for system instructions based accesses. So, skip the lock register access in such cases. Link: https://lore.kernel.org/r/20210110224850.1880240-15-suzuki.poulose@arm.com Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210201181351.1475223-17-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
d02dfac3 |
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01-Feb-2021 |
Suzuki K Poulose <suzuki.poulose@arm.com> |
coresight: etm4x: Define DEVARCH register fields Define the fields of the DEVARCH register for identifying a component as an ETMv4.x unit. Going forward, we use the DEVARCH register for the component identification, rather than the TRCIDR3. Link: https://lore.kernel.org/r/20210110224850.1880240-14-suzuki.poulose@arm.com Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210201181351.1475223-16-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
03336d0f |
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01-Feb-2021 |
Suzuki K Poulose <suzuki.poulose@arm.com> |
coresight: etm4x: Add sysreg access helpers ETM architecture defines the system instructions for accessing via register accesses. Add basic support for accessing a given register via system instructions. We split the list of registers as : 1) Accessible only from memory mapped interface 2) Accessible from system register instructions. All registers are accessible via the memory-mapped interface. However, some registers are not accessible via the system instructions. This list is then used to further filter out the files we expose via sysfs. Link: https://lore.kernel.org/r/20210110224850.1880240-12-suzuki.poulose@arm.com Cc: Mike Leach <mike.leach@linaro.org> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210201181351.1475223-14-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
f5bd5236 |
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01-Feb-2021 |
Suzuki K Poulose <suzuki.poulose@arm.com> |
coresight: etm4x: Convert all register accesses Convert all register accesses from etm4x driver to use a wrapper to allow switching the access at runtime with little overhead. co-developed by sed tool ;-), mostly equivalent to : s/readl\(_relaxed\)\?(drvdata->base + \(.*\))/etm4x_\1_read32(csdev, \2) s/writel\(_relaxed\)\?(\(.*\), drvdata->base + \(.*\))/etm4x_\1_write32(csdev, \2, \3) We don't want to replace them with the csdev_access_* to avoid a function call for every register access for system register access. This is a prepartory step to add system register access later where the support is available. Link: https://lore.kernel.org/r/20210110224850.1880240-9-suzuki.poulose@arm.com Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210201181351.1475223-11-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
8ce00296 |
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01-Feb-2021 |
Suzuki K Poulose <suzuki.poulose@arm.com> |
coresight: Convert claim/disclaim operations to use access wrappers Convert the generic CLAIM tag management APIs to use the device access layer abstraction. Link: https://lore.kernel.org/r/20210110224850.1880240-7-suzuki.poulose@arm.com Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210201181351.1475223-9-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
02005282 |
|
01-Feb-2021 |
Suzuki K Poulose <suzuki.poulose@arm.com> |
coresight: Convert coresight_timeout to use access abstraction Convert the generic routines to use the new access abstraction layer gradually, starting with coresigth_timeout. Link: https://lore.kernel.org/r/20210110224850.1880240-6-suzuki.poulose@arm.com Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210201181351.1475223-8-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
6e736c60 |
|
01-Feb-2021 |
Suzuki K Poulose <suzuki.poulose@arm.com> |
coresight: Introduce device access abstraction We are about to introduce support for sysreg access to ETMv4.4+ component. Since there are generic routines that access the registers (e.g, CS_LOCK/UNLOCK , claim/disclaim operations, timeout) and in order to preserve the logic of these operations at a single place we introduce an abstraction layer for the accesses to a given device. Link: https://lore.kernel.org/r/20210110224850.1880240-4-suzuki.poulose@arm.com Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210201181351.1475223-6-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
df81b438 |
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01-Feb-2021 |
Suzuki K Poulose <suzuki.poulose@arm.com> |
coresight: etm4x: Skip accessing TRCPDCR in save/restore When the ETM is affected by Qualcomm errata, modifying the TRCPDCR could cause the system hang. Even though this is taken care of during enable/disable ETM, the ETM state save/restore could still access the TRCPDCR. Make sure we skip the access during the save/restore. Found by code inspection. Link: https://lore.kernel.org/r/20210110224850.1880240-3-suzuki.poulose@arm.com Fixes: 02510a5aa78d ("coresight: etm4x: Add support to skip trace unit power up") Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Cc: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Cc: Tingwei Zhang <tingwei@codeaurora.org> Tested-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Reviewed-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210201181351.1475223-5-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
f6a18f35 |
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01-Feb-2021 |
Suzuki K Poulose <suzuki.poulose@arm.com> |
coresight: etm4x: Handle access to TRCSSPCICRn TRCSSPCICR<n> is present only if all of the following are true: TRCIDR4.NUMSSCC > n. TRCIDR4.NUMPC > 0b0000 . TRCSSCSR<n>.PC == 0b1 Add a helper function to check all the conditions. Link: https://lore.kernel.org/r/20210110224850.1880240-2-suzuki.poulose@arm.com Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210201181351.1475223-4-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
b8336ad9 |
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01-Feb-2021 |
Chunyan Zhang <chunyan.zhang@unisoc.com> |
coresight: etm4x: add AMBA id for Cortex-A55 and Cortex-A75 Add AMBA UCI id to support Cortex-A55(Ananke) and Cortex-A75(Promethus). Reviewed by: Mike Leach <mike.leach@linaro.org> Link: https://lore.kernel.org/r/20210118065549.197489-1-zhang.lyra@gmail.com Signed-off-by: Bin Ji <bin.ji@unisoc.com> Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210201181351.1475223-3-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
3fd269e7 |
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26-Jan-2021 |
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> |
amba: Make the remove callback return void All amba drivers return 0 in their remove callback. Together with the driver core ignoring the return value anyhow, it doesn't make sense to return a value here. Change the remove prototype to return void, which makes it explicit that returning an error value doesn't work as expected. This simplifies changing the core remove callback to return void, too. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> # for drivers/memory Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com> # for hwtracing/coresight Acked-By: Vinod Koul <vkoul@kernel.org> # for dmaengine Acked-by: Guenter Roeck <linux@roeck-us.net> # for watchdog Acked-by: Wolfram Sang <wsa@kernel.org> # for I2C Acked-by: Takashi Iwai <tiwai@suse.de> # for sound Acked-by: Vladimir Zapolskiy <vz@mleia.com> # for memory/pl172 Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Link: https://lore.kernel.org/r/20210126165835.687514-5-u.kleine-koenig@pengutronix.de Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
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#
e7255092 |
|
08-Dec-2020 |
Qi Liu <liuqi115@huawei.com> |
coresight: etm4x: Modify core-commit to avoid HiSilicon ETM overflow The ETM device can't keep up with the core pipeline when cpu core is at full speed. This may cause overflow within core and its ETM. This is a common phenomenon on ETM devices. On HiSilicon Hip08 platform, a specific feature is added to set core pipeline. So commit rate can be reduced manually to avoid ETM overflow. Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Qi Liu <liuqi115@huawei.com> [Modified changelog title and Kconfig description] Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20201208182651.1597945-4-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
45fe7bef |
|
08-Dec-2020 |
Arnd Bergmann <arnd@arndb.de> |
coresight: remove broken __exit annotations Functions that are annotated __exit are discarded for built-in drivers, but the .remove callback in a device driver must still be kept around to allow bind/unbind operations. There is now a linker warning for the discarded symbol references: `tmc_remove' referenced in section `.data' of drivers/hwtracing/coresight/coresight-tmc-core.o: defined in discarded section `.exit.text' of drivers/hwtracing/coresight/coresight-tmc-core.o `tpiu_remove' referenced in section `.data' of drivers/hwtracing/coresight/coresight-tpiu.o: defined in discarded section `.exit.text' of drivers/hwtracing/coresight/coresight-tpiu.o `etb_remove' referenced in section `.data' of drivers/hwtracing/coresight/coresight-etb10.o: defined in discarded section `.exit.text' of drivers/hwtracing/coresight/coresight-etb10.o `static_funnel_remove' referenced in section `.data' of drivers/hwtracing/coresight/coresight-funnel.o: defined in discarded section `.exit.text' of drivers/hwtracing/coresight/coresight-funnel.o `dynamic_funnel_remove' referenced in section `.data' of drivers/hwtracing/coresight/coresight-funnel.o: defined in discarded section `.exit.text' of drivers/hwtracing/coresight/coresight-funnel.o `static_replicator_remove' referenced in section `.data' of drivers/hwtracing/coresight/coresight-replicator.o: defined in discarded section `.exit.text' of drivers/hwtracing/coresight/coresight-replicator.o `dynamic_replicator_remove' referenced in section `.data' of drivers/hwtracing/coresight/coresight-replicator.o: defined in discarded section `.exit.text' of drivers/hwtracing/coresight/coresight-replicator.o `catu_remove' referenced in section `.data' of drivers/hwtracing/coresight/coresight-catu.o: defined in discarded section `.exit.text' of drivers/hwtracing/coresight/coresight-catu.o Remove all those annotations. Fixes: 8b0cf82677d1 ("coresight: stm: Allow to build coresight-stm as a module") Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20201208182651.1597945-3-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
60c519c5 |
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27-Nov-2020 |
Suzuki K Poulose <suzuki.poulose@arm.com> |
coresight: etm4x: Handle TRCVIPCSSCTLR accesses TRCVIPCSSCTLR is not present if the TRCIDR4.NUMPC > 0. Thus we should only access the register if it is present, preventing any undesired behavior. Cc: stable@vger.kernel.org Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20201127175256.1092685-8-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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6288b4ce |
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27-Nov-2020 |
Suzuki K Poulose <suzuki.poulose@arm.com> |
coresight: etm4x: Fix accesses to TRCPROCSELR TRCPROCSELR is not implemented if the TRCIDR3.NUMPROC == 0. Skip accessing the register in such cases. Cc: stable@vger.kernel.org Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20201127175256.1092685-7-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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4e218727 |
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27-Nov-2020 |
Suzuki K Poulose <suzuki.poulose@arm.com> |
coresight: etm4x: Update TRCIDR3.NUMPROCS handling to match v4.2 Since ETMv4.2, TRCIDR3.NUMPROCS has been extended to a 5bit field by encoding the top 2 bits[4:3] in TRCIDR3.[13:12], which were RES0. Fix the driver to compute the field correctly for ETMv4.2+ Cc: Mike Leach <mike.leach@linaro.org> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20201127175256.1092685-6-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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f2603b22 |
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27-Nov-2020 |
Suzuki K Poulose <suzuki.poulose@arm.com> |
coresight: etm4x: Fix accesses to TRCCIDCTLR1 The TRCCIDCTLR1 is only implemented if TRCIDR4.NUMCIDC > 4. Don't touch the register if it is not implemented. Cc: stable@vger.kernel.org Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20201127175256.1092685-5-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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93dd6440 |
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27-Nov-2020 |
Suzuki K Poulose <suzuki.poulose@arm.com> |
coresight: etm4x: Fix accesses to TRCVMIDCTLR1 TRCVMIDCTRL1 is only implemented only if the TRCIDR4.NUMVMIDC > 4. We must not touch the register otherwise. Cc: stable@vger.kernel.org Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20201127175256.1092685-4-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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ac0f82b1 |
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27-Nov-2020 |
Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> |
coresight: etm4x: Skip setting LPOVERRIDE bit for qcom, skip-power-up There is a bug on the systems supporting to skip power up (qcom,skip-power-up) where setting LPOVERRIDE bit(low-power state override behaviour) will result in CPU hangs/lockups even on the implementations which supports it. So skip setting the LPOVERRIDE bit for such platforms. Fixes: 02510a5aa78d ("coresight: etm4x: Add support to skip trace unit power up") Cc: stable@vger.kernel.org Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20201127175256.1092685-2-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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34773262 |
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28-Sep-2020 |
Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> |
coresight: etm4x: Fix save and restore of TRCVMIDCCTLR1 register In commit f188b5e76aae ("coresight: etm4x: Save/restore state across CPU low power states"), mistakenly TRCVMIDCCTLR1 register value was saved in trcvmidcctlr0 state variable which is used to store TRCVMIDCCTLR0 register value in etm4x_cpu_save() and then same value is written back to both TRCVMIDCCTLR0 and TRCVMIDCCTLR1 in etm4x_cpu_restore(). There is already a trcvmidcctlr1 state variable available for TRCVMIDCCTLR1, so use it. Fixes: f188b5e76aae ("coresight: etm4x: Save/restore state across CPU low power states") Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20200928163513.70169-26-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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22a550a3 |
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28-Sep-2020 |
Kim Phillips <kim.phillips@arm.com> |
coresight: etm4x: Allow etm4x to be built as a module Allow to build coresight-etm4x as a module, for ease of development. - Kconfig becomes a tristate, to allow =m - append -core to source file name to allow module to be called coresight-etm4x by the Makefile - add an etm4_remove function, for module unload - add a MODULE_DEVICE_TABLE for autoloading on boot - delay advertising the per-cpu etmdrvdata - protect etmdrvdata[] by modifying it on relevant CPU Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Leo Yan <leo.yan@linaro.org> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Randy Dunlap <rdunlap@infradead.org> Cc: Suzuki K Poulose <Suzuki.Poulose@arm.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Russell King <linux@armlinux.org.uk> Tested-by: Mike Leach <mike.leach@linaro.org> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Kim Phillips <kim.phillips@arm.com> Signed-off-by: Tingwei Zhang <tingwei@codeaurora.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20200928163513.70169-11-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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