Searched refs:SrcRegs (Results 1 - 7 of 7) sorted by last modified time
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86MCInstLower.cpp | 1458 Register SrcRegs[] = {0, 0}; local 1468 SrcRegs[I] = getX86SubSuperRegister(Op->getReg(), 64); 1469 if (SrcRegs[I] != DestRegs[I]) { 1479 // FIXME: This doesn't work if one of the later SrcRegs is equal to an 1483 if (SrcRegs[I] != DestRegs[I]) 1485 MCInstBuilder(X86::MOV64rr).addReg(DestRegs[I]).addReg(SrcRegs[I])); 1556 Register SrcRegs[] = {0, 0, 0}; local 1566 SrcRegs[I] = getX86SubSuperRegister(Op->getReg(), 64); 1567 if (SrcRegs[I] != DestRegs[I]) { 1582 // FIXME: This doesn't work if one of the later SrcRegs i [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPURegisterBankInfo.cpp | 1125 SmallVector<unsigned, 1> SrcRegs(OpdMapper.getVRegs(1)); 1128 if (SrcRegs.empty()) { 1133 SrcRegs.push_back(MI.getOperand(1).getReg()); 1145 Register BasePtrReg = SrcRegs[0];
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | PeepholeOptimizer.cpp | 750 /// Insert a PHI instruction with incoming edges \p SrcRegs that are 757 const SmallVectorImpl<RegSubRegPair> &SrcRegs, 759 assert(!SrcRegs.empty() && "No sources to create a PHI instruction?"); 761 const TargetRegisterClass *NewRC = MRI.getRegClass(SrcRegs[0].Reg); 764 assert(SrcRegs[0].SubReg == 0 && "should not have subreg operand"); 771 for (const RegSubRegPair &RegPair : SrcRegs) { 756 insertPHI(MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const SmallVectorImpl<RegSubRegPair> &SrcRegs, MachineInstr &OrigPHI) argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | LegalizerHelper.cpp | 914 SmallVector<SmallVector<Register, 2>, 2> SrcRegs; local 916 SrcRegs.resize(MI.getNumOperands() / 2); 922 SrcRegs[i / 2]); 931 MIB.addUse(SrcRegs[j / 2][i]).add(MI.getOperand(j + 1)); 1024 SmallVector<Register, 2> SrcRegs; local 1030 SrcRegs.push_back(SrcReg); 1034 MIRBuilder.buildUnmerge(SrcRegs, MI.getOperand(1).getReg()); 1046 DstRegs.push_back(SrcRegs[i]); 1065 {SrcRegs[i], SizeInBits % NarrowTy.getScalarSizeInBits()}) 1084 SmallVector<Register, 2> SrcRegs, DstReg local 2569 SmallVector<Register, 4> SrcRegs, DstRegs; local 3511 SmallVector<Register, 2> SrcRegs, DstRegs; local 3578 SmallVector<Register, 2> SrcRegs, DstRegs; local [all...] |
H A D | IRTranslator.cpp | 975 ArrayRef<Register> SrcRegs = getOrCreateVRegs(*Src); local 981 DstRegs[i] = SrcRegs[Idx++]; 992 ArrayRef<Register> SrcRegs = getOrCreateVRegs(*Src); local 1000 DstRegs[i] = SrcRegs[i];
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H A D | CallLowering.cpp | 130 Register CallLowering::packRegs(ArrayRef<Register> SrcRegs, Type *PackedTy, argument 132 assert(SrcRegs.size() > 1 && "Nothing to pack"); 142 assert(LLTs.size() == SrcRegs.size() && "Regs / types mismatch"); 146 for (unsigned i = 0; i < SrcRegs.size(); ++i) { 148 MIRBuilder.buildInsert(NewDst, Dst, SrcRegs[i], Offsets[i]);
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
H A D | CallLowering.h | 187 /// Generate instructions for packing \p SrcRegs into one big register 190 /// \param SrcRegs should contain one virtual register for each base type in 194 Register packRegs(ArrayRef<Register> SrcRegs, Type *PackedTy,
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