Searched refs:SMU__NUM_SCLK_DPM_STATE (Results 1 - 22 of 22) sorted by relevance

/linux-master/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dci_smumgr.h26 #define SMU__NUM_SCLK_DPM_STATE 8 macro
/linux-master/drivers/gpu/drm/radeon/
H A Dkv_dpm.h26 #define SMU__NUM_SCLK_DPM_STATE 8 macro
131 SMU7_Fusion_GraphicsLevel graphics_level[SMU__NUM_SCLK_DPM_STATE];
H A Dsmu7.h41 #define SMU7_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE // SCLK + SQ DPM + ULV
H A Dci_dpm.h29 #define SMU__NUM_SCLK_DPM_STATE 8 macro
H A Dsmu7_fusion.h224 SMU7_Fusion_GraphicsLevel GraphicsLevel[SMU__NUM_SCLK_DPM_STATE];
H A Dsmu7_discrete.h226 SMU7_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
H A Dkv_dpm.c2607 if (current_index >= SMU__NUM_SCLK_DPM_STATE) {
2629 if (current_index >= SMU__NUM_SCLK_DPM_STATE) {
/linux-master/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dkv_dpm.h26 #define SMU__NUM_SCLK_DPM_STATE 8 macro
157 SMU7_Fusion_GraphicsLevel graphics_level[SMU__NUM_SCLK_DPM_STATE];
H A Dkv_dpm.c2864 if (current_index >= SMU__NUM_SCLK_DPM_STATE) {
3271 if (pl_index < SMU__NUM_SCLK_DPM_STATE) {
/linux-master/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dsmu7.h41 #define SMU7_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE // SCLK + SQ DPM + ULV
H A Dsmu71.h31 #define SMU__NUM_SCLK_DPM_STATE 8 macro
61 #define SMU71_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE
H A Dsmu72.h31 #define SMU__NUM_SCLK_DPM_STATE 8 macro
109 #define SMU72_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE /* SCLK + SQ DPM + ULV */
H A Dsmu73.h90 #define SMU__NUM_SCLK_DPM_STATE 8 macro
105 #define SMU73_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE // SCLK + SQ DPM + ULV
H A Dsmu7_fusion.h224 SMU7_Fusion_GraphicsLevel GraphicsLevel[SMU__NUM_SCLK_DPM_STATE];
H A Dsmu74.h32 #define SMU__NUM_SCLK_DPM_STATE 8 macro
134 #define SMU74_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE /* SCLK + SQ DPM + ULV */
H A Dsmu75.h40 #define SMU__NUM_SCLK_DPM_STATE 8 macro
55 #define SMU75_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE
H A Dsmu71_discrete.h179 SMU71_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
H A Dsmu7_discrete.h235 SMU7_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
H A Dsmu72_discrete.h166 SMU72_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
H A Dsmu74_discrete.h179 SMU74_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
H A Dsmu75_discrete.h192 SMU75_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
H A Dsmu73_discrete.h150 SMU73_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];

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