Searched refs:SMU__NUM_PCIE_DPM_LEVELS (Results 1 - 11 of 11) sorted by relevance

/linux-master/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dci_smumgr.h29 #define SMU__NUM_PCIE_DPM_LEVELS 8 macro
/linux-master/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dsmu7.h44 #define SMU7_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS // PCIe speed and number of lanes.
H A Dsmu71.h30 #define SMU__NUM_PCIE_DPM_LEVELS 8 macro
64 #define SMU71_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS
H A Dsmu72.h34 #define SMU__NUM_PCIE_DPM_LEVELS 8 macro
112 #define SMU72_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS /* PCIe speed and number of lanes. */
H A Dsmu73.h93 #define SMU__NUM_PCIE_DPM_LEVELS 8 macro
108 #define SMU73_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS // PCIe speed and number of lanes.
H A Dsmu74.h35 #define SMU__NUM_PCIE_DPM_LEVELS 8 macro
137 #define SMU74_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS /* PCIe speed and number of lanes */
H A Dsmu75.h43 #define SMU__NUM_PCIE_DPM_LEVELS 8 macro
58 #define SMU75_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS
/linux-master/drivers/gpu/drm/radeon/
H A Dsmu7.h44 #define SMU7_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS // PCIe speed and number of lanes.
H A Dkv_dpm.h29 #define SMU__NUM_PCIE_DPM_LEVELS 0 /* ??? */ macro
H A Dci_dpm.h32 #define SMU__NUM_PCIE_DPM_LEVELS 8 macro
/linux-master/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dkv_dpm.h29 #define SMU__NUM_PCIE_DPM_LEVELS 0 /* ??? */ macro

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