Searched refs:SET_BIT (Results 1 - 17 of 17) sorted by relevance

/linux-master/drivers/video/fbdev/kyro/
H A DSTG4000VTG.c34 tmp |= SET_BIT(8);
43 tmp = (STG_READ_REG(DACSyncCtrl)) | SET_BIT(0) | SET_BIT(2);
53 tmp = ((STG_READ_REG(DACSyncCtrl)) | SET_BIT(31));
157 tmp = STG_READ_REG(DACSyncCtrl) | SET_BIT(3) | SET_BIT(1);
H A DSTG4000Ramdac.c104 tmp &= ~SET_BIT(31);
152 tmp = (STG_READ_REG(DACStreamCtrl)) & ~SET_BIT(0);
161 tmp = (STG_READ_REG(DACStreamCtrl)) | SET_BIT(0);
H A DSTG4000InitDevice.c296 tmp |= SET_BIT(14);
306 tmp |= SET_BIT(14);
314 tmp = ((STG_READ_REG(Thread0Enable)) | SET_BIT(0));
318 tmp = ((STG_READ_REG(Thread1Enable)) | SET_BIT(0));
H A DSTG4000OverlayDevice.c181 tmp |= SET_BIT(31); /* Overlay format to Planer */
293 tmp |= SET_BIT(7);
298 tmp |= SET_BIT(1); /* video stream */
H A DSTG4000Reg.h31 #define SET_BIT(n) (1<<(n)) macro
/linux-master/drivers/net/ethernet/sfc/siena/
H A Dmcdi_port_common.c115 #define SET_BIT(name) __set_bit(ETHTOOL_LINK_MODE_ ## name ## _BIT, \ macro
121 SET_BIT(Backplane);
123 SET_BIT(1000baseKX_Full);
125 SET_BIT(10000baseKX4_Full);
127 SET_BIT(40000baseKR4_Full);
133 SET_BIT(FIBRE);
135 SET_BIT(1000baseT_Full);
136 SET_BIT(1000baseX_Full);
139 SET_BIT(10000baseCR_Full);
140 SET_BIT(1000
185 #undef SET_BIT macro
[all...]
/linux-master/drivers/net/ethernet/sfc/
H A Dmcdi_port_common.c114 #define SET_BIT(name) __set_bit(ETHTOOL_LINK_MODE_ ## name ## _BIT, \ macro
120 SET_BIT(Backplane);
122 SET_BIT(1000baseKX_Full);
124 SET_BIT(10000baseKX4_Full);
126 SET_BIT(40000baseKR4_Full);
132 SET_BIT(FIBRE);
134 SET_BIT(1000baseT_Full);
135 SET_BIT(1000baseX_Full);
138 SET_BIT(10000baseCR_Full);
139 SET_BIT(1000
184 #undef SET_BIT macro
[all...]
/linux-master/drivers/net/ethernet/apm/xgene/
H A Dxgene_enet_ring2.c19 ring_cfg[3] |= SET_BIT(X2_DEQINTEN);
31 ring_cfg[5] |= SET_BIT(X2_QBASE_AM) | SET_BIT(X2_MSG_AM);
H A Dxgene_enet_main.c106 SET_BIT(COHERENT));
157 SET_BIT(COHERENT));
360 *hopinfo |= SET_BIT(ET) | SET_VAL(MSS, mss_index);
373 SET_BIT(IC) |
374 SET_BIT(TYPE_ETH_WORK_MESSAGE);
447 SET_BIT(COHERENT));
/linux-master/drivers/usb/storage/
H A Drealtek_cr.c120 #define SET_BIT(data, idx) ((data) |= 1 << (idx)) macro
574 SET_BIT(value, 2);
579 SET_BIT(value, 7);
592 SET_BIT(value, 2);
639 SET_BIT(value, 2);
655 SET_BIT(value, 0);
657 SET_BIT(value, 2);
671 SET_BIT(value, 0);
672 SET_BIT(value, 7);
676 SET_BIT(valu
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/linux-master/drivers/scsi/sym53c8xx_2/
H A Dsym_nvram.c235 #define SET_BIT 0 macro
248 case SET_BIT:
272 S24C16_set_bit(np, 1, gpreg, SET_BIT);
284 S24C16_set_bit(np, 1, gpreg, SET_BIT);
294 S24C16_set_bit(np, write_bit, gpreg, SET_BIT);
488 #undef SET_BIT macro
/linux-master/include/linux/mdio/
H A Dmdio-xgene.h111 #define SET_BIT(field) \ macro
/linux-master/drivers/crypto/intel/qat/qat_common/
H A Dqat_hal.c154 #define SET_BIT(wrd, bit) ((wrd) | 1 << (bit)) macro
170 SET_BIT(csr, CE_INUSE_CONTEXTS_BITPOS) :
185 SET_BIT(csr, CE_NN_MODE_BITPOS) :
205 SET_BIT(csr, CE_LMADDR_0_GLOBAL_BITPOS) :
210 SET_BIT(csr, CE_LMADDR_1_GLOBAL_BITPOS) :
215 SET_BIT(csr, CE_LMADDR_2_GLOBAL_BITPOS) :
220 SET_BIT(csr, CE_LMADDR_3_GLOBAL_BITPOS) :
241 SET_BIT(csr, CE_T_INDEX_GLOBAL_BITPOS) :
/linux-master/drivers/staging/rts5208/
H A Drtsx_scsi.c421 SET_BIT(chip->lun_mc, lun);
857 SET_BIT(chip->lun_mc, lun);
1058 SET_BIT(chip->lun_mc, lun);
H A Drtsx_chip.h325 #define SET_BIT(data, idx) ((data) |= 1 << (idx)) macro
H A Dsd.c3770 SET_BIT(chip->lun_mc, lun);
/linux-master/drivers/i2c/busses/
H A Di2c-qup.c120 #define SET_BIT 0x1 macro

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