Searched refs:R_BCM1480_MC_CSX_ROW1 (Results 1 - 2 of 2) sorted by path

/broadcom-cfe-1.4.2/cfe/arch/mips/chipset/sibyte/include/
H A Dbcm1480_regs.h124 #define R_BCM1480_MC_CSX_ROW1 0x0000000020 /* relative to CSX_BASE */ macro
/broadcom-cfe-1.4.2/cfe/arch/mips/cpu/bcm1480/src/
H A Dbcm1480_draminit.c3095 WRITECSR((mcbase+R_BCM1480_MC_CSX_BASE+R_BCM1480_MC_CSX_ROW1+col_row_spacing),
3618 WRITECSR((mcbase+R_BCM1480_MC_CSX_BASE+R_BCM1480_MC_CSX_ROW1),
3623 WRITECSR((mcbase+R_BCM1480_MC_CSX_BASE+R_BCM1480_MC_CSX_ROW1+BCM1480_MC_CSX_SPACING),

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