Searched refs:RX0 (Results 1 - 19 of 19) sorted by relevance

/linux-master/arch/x86/crypto/
H A Dblowfish-x86_64-asm_64.S24 #define RX0 %rax define
60 rorq $16, RX0; \
63 rolq $16, RX0; \
68 rolq $32, RX0; \
71 xorq RT0, RX0;
74 xorq p+4*(n)(CTX), RX0;
85 xorq RT0, RX0;
94 movq (RIO), RX0; \
95 rorq $32, RX0; \
96 bswapq RX0;
[all...]
H A Dsm4-aesni-avx-asm_64.S22 #define RX0 %xmm0 define
189 vbroadcastss (4*(round))(%rdi), RX0; \
190 vpxor s1, RX0, RX0; \
191 vpxor s2, RX0, RX0; \
192 vpxor s3, RX0, RX0; /* s1 ^ s2 ^ s3 ^ rk */ \
195 transform_pre(RX0, RTMP4, RB0, MASK_4BIT, RTMP0); \
196 vaesenclast MASK_4BIT, RX0, RX
[all...]
H A Dsm4-aesni-avx2-asm_64.S23 #define RX0 %ymm0 define
183 vpbroadcastd (4*(round))(%rdi), RX0; \
186 vmovdqa RX0, RX1; \
187 vpxor s1, RX0, RX0; \
188 vpxor s2, RX0, RX0; \
189 vpxor s3, RX0, RX0; /* s1 ^ s2 ^ s3 ^ rk */ \
197 transform_pre(RX0, RTMP
[all...]
H A Dtwofish-avx-x86_64-asm_64.S47 #define RX0 %xmm8 define
175 round_head_2(a, b, RX0, RY0, RX1, RY1); \
176 encround_tail(a ## 1, b ## 1, c ## 1, d ## 1, RX0, RY0, prerotate); \
183 round_head_2(a, b, RX0, RY0, RX1, RY1); \
184 decround_tail(a ## 1, b ## 1, c ## 1, d ## 1, RX0, RY0, prerotate); \
245 inpack_blocks(RA1, RB1, RC1, RD1, RK1, RX0, RY0, RK2);
248 inpack_blocks(RA2, RB2, RC2, RD2, RK1, RX0, RY0, RK2);
266 outunpack_blocks(RC1, RD1, RA1, RB1, RK1, RX0, RY0, RK2);
267 outunpack_blocks(RC2, RD2, RA2, RB2, RK1, RX0, RY0, RK2);
285 inpack_blocks(RC1, RD1, RA1, RB1, RK1, RX0, RY
[all...]
H A Dtwofish-x86_64-asm_64-3way.S53 #define RX0 %r8 define
146 enc_round_end(ab ## 0, RX0, RY0, n); \
153 dec_round_end(ba ## 0, RX0, RY0, n); \
/linux-master/arch/arm64/crypto/
H A Dsm4-neon-core.S26 #define RX0 v12 define
97 dup RX0.4s, RKEY.s[round]; \
100 eor RX0.16b, RX0.16b, s1.16b; \
101 eor RX0.16b, RX0.16b, RTMP1.16b; \
105 tbl RTMP0.16b, {v16.16b-v19.16b}, RX0.16b; \
106 sub RX0.16b, RX0.16b, RTMP3.16b; \
107 tbx RTMP0.16b, {v20.16b-v23.16b}, RX0
[all...]
/linux-master/drivers/pinctrl/renesas/
H A Dpfc-r8a779f0.c48 #define GPSR0_6 F_(RX0, IP0SR0_27_24)
130 #define IP0SR0_27_24 FM(RX0) FM(HRX1) F_(0, 0) FM(MSIOF1_RXD) F_(0, 0) FM(TSN1_AVTP_MATCH_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358 PINMUX_IPSR_GPSR(IP0SR0_27_24, RX0),
976 /* RX0, TX0 */
1793 { RCAR_GP_PIN(0, 6), 24, 3 }, /* RX0 */
1944 [ 6] = RCAR_GP_PIN(0, 6), /* RX0 */
H A Dpfc-r8a77970.c225 #define IP7_23_20 FM(SCL2) FM(DU_DB0) FM(TCLK1_A) FM(WE1_N) FM(RX0) FM(MSIOF0_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
681 PINMUX_IPSR_GPSR(IP7_23_20, RX0),
H A Dpfc-r8a77980.c259 #define IP7_23_20 FM(SCL2) F_(0, 0) F_(0, 0) FM(WE1_N) FM(RX0) FM(HRX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
745 PINMUX_IPSR_GPSR(IP7_23_20, RX0),
1737 /* RX0, TX0 */
H A Dpfc-r8a77951.c209 #define GPSR5_1 F_(RX0, IP11_31_28)
354 #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
1184 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
5791 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
6044 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
H A Dpfc-r8a77965.c214 #define GPSR5_1 F_(RX0, IP11_31_28)
359 #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
1194 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
5984 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
6237 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
H A Dpfc-r8a7796.c214 #define GPSR5_1 F_(RX0, IP11_31_28)
359 #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
1191 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
5743 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
5996 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
H A Dpfc-r8a7792.c459 PINMUX_SINGLE(RX0),
2987 [14] = RCAR_GP_PIN(10, 14), /* RX0 */
H A Dpfc-r8a779a0.c358 #define IP0SR1_7_4 FM(HRX0) FM(RX0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
795 PINMUX_IPSR_GPSR(IP0SR1_7_4, RX0),
2408 /* RX0, TX0 */
H A Dpfc-r8a779g0.c324 #define IP2SR1_3_0 FM(HRX0) FM(RX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
842 PINMUX_IPSR_GPSR(IP2SR1_3_0, RX0),
2242 /* RX0, TX0 */
H A Dpfc-r8a779h0.c311 #define IP2SR1_3_0 FM(HRX0) FM(RX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
787 PINMUX_IPSR_GPSR(IP2SR1_3_0, RX0),
2210 /* RX0, TX0 */
H A Dpfc-r8a7779.c1205 PINMUX_IPSR_MSEL(IP8_15_12, RX0, SEL_SCIF0_0),
H A Dpfc-r8a7791.c935 PINMUX_IPSR_MSEL(IP2_12_10, RX0, SEL_SCIF0_0),
H A Dpfc-r8a7790.c1597 PINMUX_IPSR_MSEL(IP14_8_6, RX0, SEL_SCIF0_0),

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