/linux-master/sound/soc/tegra/ |
H A D | tegra210_mvc.h | 92 #define REG_SIZE 4 macro 94 #define TEGRA210_MVC_REG_OFFSET(reg, i) (reg + (REG_SIZE * i)) 96 #define TEGRA210_MVC_GET_CHAN(reg, base) (((reg) - (base)) / REG_SIZE)
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/linux-master/drivers/irqchip/ |
H A D | qcom-irq-combiner.c | 24 #define REG_SIZE 32 macro 41 return reg * REG_SIZE + bit; 82 struct combiner_reg *reg = combiner->regs + data->hwirq / REG_SIZE; 84 clear_bit(data->hwirq % REG_SIZE, ®->enabled); 90 struct combiner_reg *reg = combiner->regs + data->hwirq / REG_SIZE; 92 set_bit(data->hwirq % REG_SIZE, ®->enabled); 186 (reg->bit_width > REG_SIZE)) { 192 vaddr = devm_ioremap(ctx->dev, reg->address, REG_SIZE);
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/linux-master/drivers/hwmon/ |
H A D | ultra45_env.c | 38 #define REG_SIZE 0x42UL macro 265 p->regs = of_ioremap(&op->resource[0], 0, REG_SIZE, "pic16f747"); 289 of_iounmap(&op->resource[0], p->regs, REG_SIZE); 301 of_iounmap(&op->resource[0], p->regs, REG_SIZE);
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/linux-master/drivers/pinctrl/qcom/ |
H A D | pinctrl-ipq5018.c | 12 #define REG_SIZE 0x1000 macro 31 .ctl_reg = REG_SIZE * id, \ 32 .io_reg = 0x4 + REG_SIZE * id, \ 33 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 34 .intr_status_reg = 0xc + REG_SIZE * id, \ 35 .intr_target_reg = 0x8 + REG_SIZE * id, \
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H A D | pinctrl-ipq5332.c | 12 #define REG_SIZE 0x1000 macro 31 .ctl_reg = REG_SIZE * id, \ 32 .io_reg = 0x4 + REG_SIZE * id, \ 33 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 34 .intr_status_reg = 0xc + REG_SIZE * id, \ 35 .intr_target_reg = 0x8 + REG_SIZE * id, \
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H A D | pinctrl-ipq9574.c | 12 #define REG_SIZE 0x1000 macro 31 .ctl_reg = REG_SIZE * id, \ 32 .io_reg = 0x4 + REG_SIZE * id, \ 33 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 34 .intr_status_reg = 0xc + REG_SIZE * id, \ 35 .intr_target_reg = 0x8 + REG_SIZE * id, \
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H A D | pinctrl-sdx55.c | 12 #define REG_SIZE 0x1000 macro 32 .ctl_reg = REG_SIZE * id, \ 33 .io_reg = 0x4 + REG_SIZE * id, \ 34 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 35 .intr_status_reg = 0xc + REG_SIZE * id, \ 36 .intr_target_reg = 0x8 + REG_SIZE * id, \
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H A D | pinctrl-sdx65.c | 13 #define REG_SIZE 0x1000 macro 32 .ctl_reg = REG_BASE + REG_SIZE * id, \ 33 .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \ 34 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \ 35 .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \ 36 .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
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H A D | pinctrl-ipq6018.c | 12 #define REG_SIZE 0x1000 macro 31 .ctl_reg = REG_SIZE * id, \ 32 .io_reg = 0x4 + REG_SIZE * id, \ 33 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 34 .intr_status_reg = 0xc + REG_SIZE * id, \ 35 .intr_target_reg = 0x8 + REG_SIZE * id, \
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H A D | pinctrl-ipq8074.c | 12 #define REG_SIZE 0x1000 macro 31 .ctl_reg = REG_SIZE * id, \ 32 .io_reg = 0x4 + REG_SIZE * id, \ 33 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 34 .intr_status_reg = 0xc + REG_SIZE * id, \ 35 .intr_target_reg = 0x8 + REG_SIZE * id, \
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H A D | pinctrl-sdm660.c | 25 #define REG_SIZE 0x1000 macro 45 .ctl_reg = REG_SIZE * id, \ 46 .io_reg = 0x4 + REG_SIZE * id, \ 47 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 48 .intr_status_reg = 0xc + REG_SIZE * id, \ 49 .intr_target_reg = 0x8 + REG_SIZE * id, \
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H A D | pinctrl-sdm670.c | 17 #define REG_SIZE 0x1000 macro 36 .ctl_reg = base + REG_SIZE * id, \ 37 .io_reg = base + 0x4 + REG_SIZE * id, \ 38 .intr_cfg_reg = base + 0x8 + REG_SIZE * id, \ 39 .intr_status_reg = base + 0xc + REG_SIZE * id, \ 40 .intr_target_reg = base + 0x8 + REG_SIZE * id, \
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H A D | pinctrl-msm8909.c | 13 #define REG_SIZE 0x1000 macro 32 .ctl_reg = REG_SIZE * id, \ 33 .io_reg = 0x4 + REG_SIZE * id, \ 34 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 35 .intr_status_reg = 0xc + REG_SIZE * id, \ 36 .intr_target_reg = 0x8 + REG_SIZE * id, \
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H A D | pinctrl-msm8976.c | 15 #define REG_SIZE 0x1000 macro 34 .ctl_reg = REG_BASE + REG_SIZE * id, \ 35 .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \ 36 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \ 37 .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \ 38 .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
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H A D | pinctrl-sdx75.c | 12 #define REG_SIZE 0x1000 macro 18 .ctl_reg = REG_BASE + REG_SIZE * id, \ 19 .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \ 20 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \ 21 .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \ 22 .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
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H A D | pinctrl-sm7150.c | 26 #define REG_SIZE 0x1000 macro 46 .ctl_reg = REG_SIZE * id, \ 47 .io_reg = 0x4 + REG_SIZE * id, \ 48 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 49 .intr_status_reg = 0xc + REG_SIZE * id, \ 50 .intr_target_reg = 0x8 + REG_SIZE * id, \
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H A D | pinctrl-sa8775p.c | 14 #define REG_SIZE 0x1000 macro 33 .ctl_reg = REG_BASE + REG_SIZE * id, \ 34 .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \ 35 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \ 36 .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \ 37 .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
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H A D | pinctrl-qdu1000.c | 14 #define REG_SIZE 0x1000 macro 34 .ctl_reg = REG_BASE + REG_SIZE * id, \ 35 .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \ 36 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \ 37 .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \ 38 .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
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H A D | pinctrl-qcm2290.c | 12 #define REG_SIZE 0x1000 macro 32 .ctl_reg = REG_SIZE * id, \ 33 .io_reg = 0x4 + REG_SIZE * id, \ 34 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 35 .intr_status_reg = 0xc + REG_SIZE * id, \ 36 .intr_target_reg = 0x8 + REG_SIZE * id, \
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H A D | pinctrl-sm4450.c | 12 #define REG_SIZE 0x1000 macro 32 .ctl_reg = REG_SIZE * id, \ 33 .io_reg = 0x4 + REG_SIZE * id, \ 34 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 35 .intr_status_reg = 0xc + REG_SIZE * id, \ 36 .intr_target_reg = 0x8 + REG_SIZE * id, \
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H A D | pinctrl-sc8280xp.c | 13 #define REG_SIZE 0x1000 macro 30 .ctl_reg = REG_SIZE * id, \ 31 .io_reg = 0x4 + REG_SIZE * id, \ 32 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 33 .intr_status_reg = 0xc + REG_SIZE * id, \ 34 .intr_target_reg = 0x8 + REG_SIZE * id, \
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H A D | pinctrl-sc8180x.c | 40 #define REG_SIZE 0x1000 macro 59 .ctl_reg = REG_SIZE * id + offset, \ 60 .io_reg = REG_SIZE * id + 0x4 + offset, \ 61 .intr_cfg_reg = REG_SIZE * id + 0x8 + offset, \ 62 .intr_status_reg = REG_SIZE * id + 0xc + offset,\ 63 .intr_target_reg = REG_SIZE * id + 0x8 + offset,\
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H A D | pinctrl-sdm845.c | 16 #define REG_SIZE 0x1000 macro 36 .ctl_reg = base + REG_SIZE * id, \ 37 .io_reg = base + 0x4 + REG_SIZE * id, \ 38 .intr_cfg_reg = base + 0x8 + REG_SIZE * id, \ 39 .intr_status_reg = base + 0xc + REG_SIZE * id, \ 40 .intr_target_reg = base + 0x8 + REG_SIZE * id, \
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/linux-master/arch/parisc/net/ |
H A D | bpf_jit_comp32.c | 209 emit(hppa_ldw(-REG_SIZE * (8 + (i-3)), HPPA_REG_SP, HPPA_R(i)), ctx); 228 emit(hppa_ldw(REG_SIZE * hi(reg) - offset_sp, HPPA_REG_SP, hi(tmp)), ctx); 229 emit(hppa_ldw(REG_SIZE * lo(reg) - offset_sp, HPPA_REG_SP, lo(tmp)), ctx); 251 emit(hppa_ldw(REG_SIZE * hi(reg), HPPA_REG_SP, hi(tmp)), ctx); 264 emit(hppa_stw(hi(src), REG_SIZE * hi(reg), HPPA_REG_SP), ctx); 265 emit(hppa_stw(lo(src), REG_SIZE * lo(reg), HPPA_REG_SP), ctx); 284 emit(hppa_ldw(REG_SIZE * lo(reg), HPPA_REG_SP, lo(tmp)), ctx); 309 emit(hppa_stw(lo(src), REG_SIZE * lo(reg), HPPA_REG_SP), ctx); 312 emit(hppa_stw(HPPA_REG_ZERO, REG_SIZE * hi(reg), HPPA_REG_SP), ctx); 1487 stack_adjust += NR_SAVED_REGISTERS * REG_SIZE; [all...] |
H A D | bpf_jit_comp64.c | 236 emit(hppa64_ldd_im16(-REG_SIZE * i, HPPA_REG_SP, HPPA_R(i)), ctx); 240 emit(hppa64_ldd_im16(-2*REG_SIZE, HPPA_REG_SP, HPPA_REG_RP), ctx); 243 emit(hppa64_ldd_im5(-REG_SIZE, HPPA_REG_SP, HPPA_REG_SP), ctx); 1152 emit(hppa64_std_im5 (HPPA_REG_R1, -REG_SIZE, HPPA_REG_SP), ctx); 1153 emit(hppa64_std_im16(HPPA_REG_RP, -2*REG_SIZE, HPPA_REG_SP), ctx); 1159 emit(hppa64_std_im16(HPPA_R(i), -REG_SIZE * i, HPPA_REG_SP), ctx);
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