Searched refs:PP_CONTROL (Results 1 - 11 of 11) sorted by relevance
/linux-master/drivers/gpu/drm/gma500/ |
H A D | psb_intel_lvds.c | 220 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | 231 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & 264 lvds_priv->savePP_CONTROL = REG_READ(PP_CONTROL); 315 REG_WRITE(PP_CONTROL, lvds_priv->savePP_CONTROL); 319 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | 325 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) [all...] |
H A D | cdv_intel_dp.c | 388 pp = REG_READ(PP_CONTROL); 391 REG_WRITE(PP_CONTROL, pp); 392 REG_READ(PP_CONTROL); 402 pp = REG_READ(PP_CONTROL); 405 REG_WRITE(PP_CONTROL, pp); 406 REG_READ(PP_CONTROL); 421 pp = REG_READ(PP_CONTROL); 425 REG_WRITE(PP_CONTROL, pp); 426 REG_READ(PP_CONTROL); 446 pp = REG_READ(PP_CONTROL); [all...] |
H A D | cdv_intel_lvds.c | 117 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | 128 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) &
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H A D | oaktrail_lvds.c | 46 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | 57 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) &
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H A D | oaktrail_device.c | 175 regs->psb.savePP_CONTROL = PSB_RVDC32(PP_CONTROL); 204 PSB_WVDC32(0, PP_CONTROL); 312 PSB_WVDC32(regs->psb.savePP_CONTROL, PP_CONTROL);
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H A D | cdv_device.c | 253 regs->cdv.savePP_CONTROL = REG_READ(PP_CONTROL); 336 REG_WRITE(PP_CONTROL, regs->cdv.savePP_CONTROL);
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H A D | psb_intel_reg.h | 168 #define PP_CONTROL 0x61204 macro 794 /* #define PP_CONTROL 0x61204 */
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/linux-master/drivers/gpu/drm/i915/display/ |
H A D | intel_pps_regs.h | 48 #define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL) macro
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H A D | intel_lvds.c | 164 pps->powerdown_on_reset = intel_de_read(dev_priv, PP_CONTROL(0)) & PANEL_POWER_RESET; 212 val = intel_de_read(dev_priv, PP_CONTROL(0)); 217 intel_de_write(dev_priv, PP_CONTROL(0), val); 324 intel_de_rmw(dev_priv, PP_CONTROL(0), 0, PANEL_POWER_ON); 342 intel_de_rmw(dev_priv, PP_CONTROL(0), PANEL_POWER_ON, 0);
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H A D | intel_pps.c | 280 return intel_de_read(dev_priv, PP_CONTROL(pps_idx)) & EDP_FORCE_VDD; 494 regs->pp_ctrl = PP_CONTROL(pps_idx); 499 /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */ 567 "[ENCODER:%d:%s] %s PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", 601 "[ENCODER:%d:%s] %s mask: 0x%08x value: 0x%08x PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", 610 "[ENCODER:%d:%s] %s panel status timeout: PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", 752 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] %s PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", 824 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] %s PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", 1659 intel_de_rmw(dev_priv, PP_CONTROL(pps_idx), 1717 pp_reg = PP_CONTROL( [all...] |
H A D | intel_dsi_vbt.c | 356 intel_de_rmw(dev_priv, PP_CONTROL(index), PANEL_POWER_ON, 363 intel_de_rmw(dev_priv, PP_CONTROL(index), EDP_BLC_ENABLE,
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Completed in 177 milliseconds