Searched refs:PLL_STATUS (Results 1 - 8 of 8) sorted by relevance

/linux-master/drivers/video/fbdev/omap2/omapfb/dss/
H A Dpll.c19 #define PLL_STATUS 0x0004 macro
218 if (wait_for_bit_change(base + PLL_STATUS, 0, 1) != 1)
229 u32 v = readl_relaxed(pll->base + PLL_STATUS);
301 if (wait_for_bit_change(base + PLL_STATUS, 1, 1) != 1) {
372 if (wait_for_bit_change(base + PLL_STATUS, 1, 1) != 1) {
H A Ddsi.c1201 DSI_FLD_GET(PLL_STATUS, 0, 0),
/linux-master/drivers/gpu/drm/omapdrm/dss/
H A Dpll.c19 #define PLL_STATUS 0x0004 macro
360 if (wait_for_bit_change(base + PLL_STATUS, 0, 1) != 1)
371 u32 v = readl_relaxed(pll->base + PLL_STATUS);
385 * PLL_STATUS[6] = 0 PLL_BYPASS
386 * PLL_STATUS[5] = 0 PLL_HIGHJITTER
388 * PLL_STATUS[3] = 0 PLL_LOSSREF
389 * PLL_STATUS[2] = 0 PLL_RECAL
390 * PLL_STATUS[1] = 1 PLL_LOCK
391 * PLL_STATUS[0] = 1 PLL_CTRL_RESET_DONE
472 l = readl_relaxed(base + PLL_STATUS);
[all...]
H A Ddsi.c748 DSI_FLD_GET(PLL_STATUS, 0, 0),
/linux-master/drivers/clk/imx/
H A Dclk-fracn-gppll.c39 #define PLL_STATUS 0xF0 macro
220 return readl_poll_timeout(pll->base + PLL_STATUS, val,
276 ana_mfn = readl_relaxed(pll->base + PLL_STATUS);
/linux-master/drivers/phy/ti/
H A Dphy-ti-pipe3.c25 #define PLL_STATUS 0x00000004 macro
395 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
530 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
569 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
575 dev_err(phy->dev, "Failed to power down: PLL_STATUS 0x%x\n",
/linux-master/drivers/clk/pistachio/
H A Dclk-pll.c16 #define PLL_STATUS 0x0 macro
90 while (!(pll_readl(pll, PLL_STATUS) & PLL_STATUS_LOCK))
/linux-master/drivers/clk/qcom/
H A Dclk-alpha-pll.c60 #define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS]) macro
1631 regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &val);

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