Searched refs:PHY_CTRL4 (Results 1 - 3 of 3) sorted by last modified time
/linux-master/drivers/mmc/host/ |
H A D | sdhci_am654.c | 33 #define PHY_CTRL4 0x10C macro 246 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 248 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK, 250 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK, 252 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0); 299 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 347 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 349 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 350 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0); 712 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mas [all...] |
/linux-master/drivers/phy/freescale/ |
H A D | phy-fsl-imx8mq-usb.c | 37 #define PHY_CTRL4 0x10 macro 200 value = readl(imx_phy->base + PHY_CTRL4); 204 writel(value, imx_phy->base + PHY_CTRL4);
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/linux-master/drivers/phy/qualcomm/ |
H A D | phy-qcom-usb-ss.c | 23 #define PHY_CTRL4 0x7C macro 108 qcom_ssphy_updatel(priv->base + PHY_CTRL4, LANE0_PWR_ON, LANE0_PWR_ON); 110 qcom_ssphy_updatel(priv->base + PHY_CTRL4, TST_PWR_DOWN, 0); 125 qcom_ssphy_updatel(priv->base + PHY_CTRL4, LANE0_PWR_ON, 0); 127 qcom_ssphy_updatel(priv->base + PHY_CTRL4, TST_PWR_DOWN, TST_PWR_DOWN);
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