Lines Matching refs:PHY_CTRL4
33 #define PHY_CTRL4 0x10C
246 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK,
248 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK,
250 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK,
252 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0);
299 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
347 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK,
349 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
350 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0);
712 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0);