Searched refs:PHASE (Results 1 - 10 of 10) sorted by relevance

/linux-master/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_clock_source.h60 SRII(PHASE, DP_DTO, 0),\
61 SRII(PHASE, DP_DTO, 1),\
62 SRII(PHASE, DP_DTO, 2),\
63 SRII(PHASE, DP_DTO, 3),\
64 SRII(PHASE, DP_DTO, 4),\
65 SRII(PHASE, DP_DTO, 5),\
81 SRII(PHASE, DP_DTO, 0),\
82 SRII(PHASE, DP_DTO, 1),\
90 SRII(PHASE, DP_DTO, 0),\
91 SRII(PHASE, DP_DT
228 uint32_t PHASE[MAX_PIPES]; member in struct:dce110_clk_src_regs
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H A Ddce_clock_source.c988 REG_WRITE(PHASE[inst], e->target_pixel_rate_khz * e->mult_factor);
992 REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100);
1100 clock_hz = REG_READ(PHASE[inst]);
1116 * programmed equal to DPREFCLK, in which case PHASE will be
1210 REG_WRITE(PHASE[inst], pixel_clk);
1240 REG_WRITE(PHASE[inst], e->target_pixel_rate_khz * e->mult_factor);
1244 REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100);
/linux-master/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_dccg.h53 DCCG_SRII(PHASE, DTBCLK_DTO, 0),\
54 DCCG_SRII(PHASE, DTBCLK_DTO, 1),\
55 DCCG_SRII(PHASE, DTBCLK_DTO, 2),\
56 DCCG_SRII(PHASE, DTBCLK_DTO, 3),\
/linux-master/drivers/gpu/drm/amd/display/dc/dcn314/
H A Ddcn314_dccg.h60 DCCG_SRII(PHASE, DTBCLK_DTO, 0),\
61 DCCG_SRII(PHASE, DTBCLK_DTO, 1),\
62 DCCG_SRII(PHASE, DTBCLK_DTO, 2),\
63 DCCG_SRII(PHASE, DTBCLK_DTO, 3),\
/linux-master/drivers/gpu/drm/nouveau/dispnv50/
H A Dhead917d.c44 NVVAL(NV917D, HEAD_SET_DITHER_CONTROL, PHASE, 0));
H A Dheadc37d.c100 NVVAL(NVC37D, HEAD_SET_DITHER_CONTROL, PHASE, 0));
H A Dhead507d.c62 NVVAL(NV507D, HEAD_SET_DITHER_CONTROL, PHASE, 0));
H A Dhead907d.c91 NVVAL(NV907D, HEAD_SET_DITHER_CONTROL, PHASE, 0));
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.h192 SRII_ARR_2(PHASE, DP_DTO, 0, index), \
193 SRII_ARR_2(PHASE, DP_DTO, 1, index), \
194 SRII_ARR_2(PHASE, DP_DTO, 2, index), \
195 SRII_ARR_2(PHASE, DP_DTO, 3, index), \
1233 DCCG_SRII(PHASE, DTBCLK_DTO, 0), DCCG_SRII(PHASE, DTBCLK_DTO, 1), \
1234 DCCG_SRII(PHASE, DTBCLK_DTO, 2), DCCG_SRII(PHASE, DTBCLK_DTO, 3), \
/linux-master/drivers/scsi/
H A DFlashPoint.c499 #define PHASE BIT(13) macro
1806 && !((RDW_HARPOON((ioport + hp_intstat)) & PHASE)
1833 (PROG_HLT | RSEL | PHASE | BUS_FREE));
1869 (PHASE | IUNKWN | PROG_HLT));
2057 (PROG_HLT | TIMEOUT | SEL | BUS_FREE | PHASE |
2645 WRW_HARPOON((port + hp_intstat), PHASE);
2650 WRW_HARPOON((port + hp_intstat), PHASE);
2723 (PHASE | RESET))
2805 while (!(RDW_HARPOON((port + hp_intstat)) & (PHASE | RESET)) &&
2815 WRW_HARPOON((port + hp_intstat), PHASE);
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