Searched refs:PCIEIP_REG_PCIEEP_SRIOV_CTL_E5 (Results 1 - 1 of 1) sorted by last modified time

/freebsd-11-stable/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h3172 #define PCIEIP_REG_PCIEEP_SRIOV_CTL_E5 0x000228UL //Access:RW DataWidth:0x20 // macro
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