Searched refs:PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT1_MT_E5 (Results 1 - 1 of 1) sorted by last modified time
| /freebsd-11-stable/sys/dev/qlnx/qlnxe/ | ||
| H A D | reg_addr.h | 2730 #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT1_MT_E5 (0x7<<3) // Margin type for this lane. macro [all...] |
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