Searched refs:OUT_RING (Results 1 - 10 of 10) sorted by relevance

/linux-master/drivers/gpu/drm/msm/adreno/
H A Da3xx_gpu.c48 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova));
49 OUT_RING(ring, submit->cmd[i].size);
56 OUT_RING(ring, submit->seqno);
63 OUT_RING(ring, HLSQ_FLUSH);
67 OUT_RING(ring, 0x00000000);
71 OUT_RING(ring, CACHE_FLUSH_TS | CP_EVENT_WRITE_0_IRQ);
72 OUT_RING(ring, rbmemptr(ring, fence));
73 OUT_RING(ring, submit->seqno);
78 OUT_RING(ring, CP_REG(REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG));
79 OUT_RING(rin
[all...]
H A Da5xx_gpu.c28 OUT_RING(ring, lower_32_bits(shadowptr(a5xx_gpu, ring)));
29 OUT_RING(ring, upper_32_bits(shadowptr(a5xx_gpu, ring)));
98 * we just OUT_RING() the whole thing,
103 OUT_RING(ring, ptr[i]);
138 OUT_RING(ring, 0x02);
142 OUT_RING(ring, 0);
146 OUT_RING(ring, lower_32_bits(a5xx_gpu->preempt_iova[submit->ring->id]));
147 OUT_RING(ring, upper_32_bits(a5xx_gpu->preempt_iova[submit->ring->id]));
151 OUT_RING(ring, 1);
155 OUT_RING(rin
[all...]
H A Da2xx_gpu.c30 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova));
31 OUT_RING(ring, submit->cmd[i].size);
38 OUT_RING(ring, submit->seqno);
42 OUT_RING(ring, 0x00000000);
45 OUT_RING(ring, CACHE_FLUSH_TS);
46 OUT_RING(ring, rbmemptr(ring, fence));
47 OUT_RING(ring, submit->seqno);
49 OUT_RING(ring, 0x80000000);
63 OUT_RING(ring, 0x000003ff);
65 OUT_RING(rin
[all...]
H A Da4xx_gpu.c42 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova));
43 OUT_RING(ring, submit->cmd[i].size);
50 OUT_RING(ring, submit->seqno);
57 OUT_RING(ring, HLSQ_FLUSH);
61 OUT_RING(ring, 0x00000000);
65 OUT_RING(ring, CACHE_FLUSH_TS | CP_EVENT_WRITE_0_IRQ);
66 OUT_RING(ring, rbmemptr(ring, fence));
67 OUT_RING(ring, submit->seqno);
161 OUT_RING(ring, 0x000003f7);
162 OUT_RING(rin
[all...]
H A Da6xx_gpu.c63 OUT_RING(ring, lower_32_bits(shadowptr(a6xx_gpu, ring)));
64 OUT_RING(ring, upper_32_bits(shadowptr(a6xx_gpu, ring)));
95 OUT_RING(ring, CP_REG_TO_MEM_0_REG(counter) |
98 OUT_RING(ring, lower_32_bits(iova));
99 OUT_RING(ring, upper_32_bits(iova));
121 OUT_RING(ring, 0);
125 OUT_RING(ring, 1);
130 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(lower_32_bits(ttbr)));
132 OUT_RING(ring,
135 OUT_RING(rin
[all...]
H A Da5xx_power.c231 OUT_RING(ring, 0);
235 OUT_RING(ring, lower_32_bits(a5xx_gpu->gpmu_iova));
236 OUT_RING(ring, upper_32_bits(a5xx_gpu->gpmu_iova));
237 OUT_RING(ring, a5xx_gpu->gpmu_dwords);
241 OUT_RING(ring, 1);
H A Dadreno_gpu.h536 OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));
544 OUT_RING(ring, CP_TYPE2_PKT);
551 OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
573 OUT_RING(ring, PKT4(regindx, cnt));
580 OUT_RING(ring, CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) |
/linux-master/drivers/gpu/drm/msm/
H A Dmsm_ringbuffer.h111 OUT_RING(struct msm_ringbuffer *ring, uint32_t data) function
/linux-master/drivers/gpu/drm/nouveau/
H A Dnouveau_dma.h79 OUT_RING(struct nouveau_channel *chan, int data) function
H A Dnouveau_dma.c215 OUT_RING(chan, chan->push.addr | 0x20000000);

Completed in 122 milliseconds