/haiku/src/add-ons/accelerants/ati/ |
H A D | mach64_draw.cpp | 26 OUTREG(GEN_TEST_CNTL, genTestCntl); 27 OUTREG(GEN_TEST_CNTL, genTestCntl | GUI_ENGINE_ENABLE); 31 OUTREG(BUS_CNTL, INREG(BUS_CNTL) | BUS_HOST_ERR_ACK | BUS_FIFO_ERR_ACK); 44 OUTREG(MEM_VGA_WP_SEL, 0x00010000); 45 OUTREG(MEM_VGA_RP_SEL, 0x00010000); 72 OUTREG(DP_PIX_WIDTH, dpPixWidth); 73 OUTREG(DP_CHAIN_MASK, dpChainMask); 75 OUTREG(CONTEXT_MASK, 0xffffffff); 78 OUTREG(DST_OFF_PITCH, (mode.timing.h_display / 8) << 22); 79 OUTREG(DST_Y_ [all...] |
H A D | rage128_overlay.cpp | 77 OUTREG(R128_OV0_SCALE_CNTL, 0); 78 OUTREG(R128_OV0_EXCLUSIVE_HORZ, 0); 79 OUTREG(R128_OV0_AUTO_FLIP_CNTL, 0); 80 OUTREG(R128_OV0_FILTER_CNTL, 0x0000000f); 84 OUTREG(R128_OV0_COLOUR_CNTL, brightness | saturation << 8 87 OUTREG(R128_OV0_GRAPHICS_KEY_MSK, keyMask); 88 OUTREG(R128_OV0_GRAPHICS_KEY_CLR, keyColor); 89 OUTREG(R128_OV0_KEY_CNTL, R128_GRAPHIC_KEY_FN_NE); 90 OUTREG(R128_OV0_TEST, 0); 136 OUTREG(R128_OV0_REG_LOAD_CNT [all...] |
H A D | rage128_draw.cpp | 50 OUTREG(R128_GEN_RESET_CNTL, genResetCntl | R128_SOFT_RESET_GUI); 52 OUTREG(R128_GEN_RESET_CNTL, genResetCntl & ~R128_SOFT_RESET_GUI); 56 OUTREG(R128_CLOCK_CNTL_INDEX, clockCntlIndex); 57 OUTREG(R128_GEN_RESET_CNTL, genResetCntl); 70 OUTREG(R128_SCALE_3D_CNTL, 0); 93 OUTREG(R128_DEFAULT_OFFSET, gInfo.sharedInfo->frameBufferOffset); 94 OUTREG(R128_DEFAULT_PITCH, mode.timing.h_display / 8); 97 OUTREG(R128_AUX_SC_CNTL, 0); 98 OUTREG(R128_DEFAULT_SC_BOTTOM_RIGHT, (R128_DEFAULT_SC_RIGHT_MAX 100 OUTREG(R128_SC_TOP_LEF [all...] |
H A D | mach64_overlay.cpp | 68 OUTREG(BUS_CNTL, INREG(BUS_CNTL) | BUS_EXT_REG_EN); // enable reg block 1 69 OUTREG(OVERLAY_SCALE_CNTL, SCALE_EN); // reset the video 76 OUTREG(SCALER_COLOUR_CNTL, brightness | saturation << 8 78 OUTREG(SCALER_H_COEFF0, 0x0002000); 79 OUTREG(SCALER_H_COEFF1, 0xd06200d); 80 OUTREG(SCALER_H_COEFF2, 0xd0a1c0d); 81 OUTREG(SCALER_H_COEFF3, 0xc0e1a0c); 82 OUTREG(SCALER_H_COEFF4, 0xc14140c); 113 OUTREG(OVERLAY_GRAPHICS_KEY_MSK, keyMask); 114 OUTREG(OVERLAY_GRAPHICS_KEY_CL [all...] |
H A D | mach64_cursor.cpp | 46 OUTREG(CUR_OFFSET, (si.cursorOffset >> 3) + (yOffset << 1)); 47 OUTREG(CUR_HORZ_VERT_OFF, (yOffset << 16) | xOffset); 48 OUTREG(CUR_HORZ_VERT_POSN, (y << 16) | x); 98 OUTREG(CUR_CLR0, ~0); 99 OUTREG(CUR_CLR1, 0);
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H A D | rage128_cursor.cpp | 50 OUTREG(R128_CUR_HORZ_VERT_OFF, R128_CUR_LOCK | (xOffset << 16) | yOffset); 51 OUTREG(R128_CUR_HORZ_VERT_POSN, R128_CUR_LOCK | (x << 16) | y); 52 OUTREG(R128_CUR_OFFSET, si.cursorOffset + yOffset * 16); 95 OUTREG(R128_CUR_CLR0, ~0); 96 OUTREG(R128_CUR_CLR1, 0);
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H A D | rage128_mode.cpp | 273 OUTREG(R128_OVR_CLR, 0); 274 OUTREG(R128_OVR_WID_LEFT_RIGHT, 0); 275 OUTREG(R128_OVR_WID_TOP_BOTTOM, 0); 276 OUTREG(R128_OV0_SCALE_CNTL, 0); 277 OUTREG(R128_MPP_TB_CONFIG, 0); 278 OUTREG(R128_MPP_GP_CONFIG, 0); 279 OUTREG(R128_SUBPIC_CNTL, 0); 280 OUTREG(R128_VIPH_CONTROL, 0); 281 OUTREG(R128_I2C_CNTL_1, 0); 282 OUTREG(R128_GEN_INT_CNT [all...] |
H A D | rage128_dpms.cpp | 102 OUTREG(R128_LVDS_GEN_CNTL, genCtrl); 110 OUTREG(R128_LVDS_GEN_CNTL, genCtrl); 113 OUTREG(R128_LVDS_GEN_CNTL, genCtrl); 125 OUTREG(R128_FP_GEN_CNTL, INREG(R128_FP_GEN_CNTL) 132 OUTREG(R128_FP_GEN_CNTL, INREG(R128_FP_GEN_CNTL)
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H A D | mach64_mode.cpp | 110 OUTREG(CRTC_GEN_CNTL, crtc_gen_cntl | CRTC_EXT_DISP_EN); 140 OUTREG(CRTC_GEN_CNTL, crtc_gen_cntl); // Restore register 219 OUTREG(DSP_ON_OFF, dsp_on_off); 220 OUTREG(DSP_CONFIG, dsp_config); 297 OUTREG(CRTC_GEN_CNTL, crtc_gen_cntl & ~(CRTC_EXT_DISP_EN | CRTC_EN)); 299 OUTREG(CRTC_H_TOTAL_DISP, crtc_h_total_disp); 300 OUTREG(CRTC_H_SYNC_STRT_WID, crtc_h_sync_strt_wid); 301 OUTREG(CRTC_V_TOTAL_DISP, crtc_v_total_disp); 302 OUTREG(CRTC_V_SYNC_STRT_WID, crtc_v_sync_strt_wid); 304 OUTREG(CRTC_OFF_PITC [all...] |
/haiku/headers/private/graphics/radeon/ |
H A D | mmio.h | 20 #define OUTREG( regs, addr, val ) do { *(vuint32 *)(regs + (addr)) = (val); } while( 0 ) macro 27 OUTREG( (regs), (addr), tmp ); \
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/haiku/src/add-ons/accelerants/radeon/ |
H A D | Acceleration.c | 73 OUTREG(ai->regs, RADEON_DP_GUI_MASTER_CNTL, (vc->datatype << RADEON_GMC_DST_DATATYPE_SHIFT 92 OUTREG(ai->regs, RADEON_DP_CNTL, ((xdir >= 0 ? RADEON_DST_X_LEFT_TO_RIGHT : 0) 96 OUTREG( ai->regs, RADEON_SRC_Y_X, (list->src_top << 16 ) | list->src_left); 97 OUTREG( ai->regs, RADEON_DST_Y_X, (list->dest_top << 16 ) | list->dest_left); 100 OUTREG( ai->regs, RADEON_DST_HEIGHT_WIDTH, ((list->height + 1) << 16 ) | (list->width + 1)); 166 OUTREG(ai->regs, RADEON_DP_GUI_MASTER_CNTL, ((vc->datatype << RADEON_GMC_DST_DATATYPE_SHIFT) 171 OUTREG(ai->regs, RADEON_DP_BRUSH_FRGD_CLR, colorIndex); 172 OUTREG(ai->regs, RADEON_DP_CNTL, (RADEON_DST_X_LEFT_TO_RIGHT | RADEON_DST_Y_TOP_TO_BOTTOM)); 178 OUTREG(ai->regs, RADEON_DST_Y_X, (list->top << 16) | list->left); 179 OUTREG(a [all...] |
H A D | palette.c | 41 OUTREG( ai->regs, RADEON_DAC_CNTL2, 45 OUTREG( ai->regs, RADEON_PALETTE_INDEX, 0 ); 48 OUTREG( ai->regs, RADEON_PALETTE_DATA, (i << 16) | (i << 8) | i ); 104 OUTREG( ai->regs, RADEON_DAC_CNTL2, 108 OUTREG( ai->regs, RADEON_PALETTE_INDEX, first ); 111 OUTREG( ai->regs, RADEON_PALETTE_DATA,
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H A D | crtc.c | 30 OUTREG( regs, RADEON_CRTC_H_TOTAL_DISP, values->crtc_h_total_disp ); 31 OUTREG( regs, RADEON_CRTC_H_SYNC_STRT_WID, values->crtc_h_sync_strt_wid ); 32 OUTREG( regs, RADEON_CRTC_V_TOTAL_DISP, values->crtc_v_total_disp ); 33 OUTREG( regs, RADEON_CRTC_V_SYNC_STRT_WID, values->crtc_v_sync_strt_wid ); 34 OUTREG( regs, RADEON_CRTC_OFFSET_CNTL, values->crtc_offset_cntl ); 35 OUTREG( regs, RADEON_CRTC_PITCH, values->crtc_pitch ); 44 OUTREG( regs, RADEON_CRTC2_H_TOTAL_DISP, values->crtc_h_total_disp ); 45 OUTREG( regs, RADEON_CRTC2_H_SYNC_STRT_WID, values->crtc_h_sync_strt_wid ); 46 OUTREG( regs, RADEON_CRTC2_V_TOTAL_DISP, values->crtc_v_total_disp ); 47 OUTREG( reg [all...] |
H A D | Cursor.c | 25 OUTREG( ai->regs, RADEON_CUR_CLR0, 0xffffff ); 26 OUTREG( ai->regs, RADEON_CUR_CLR1, 0 ); 28 OUTREG( ai->regs, RADEON_CUR2_CLR0, 0xffffff ); 29 OUTREG( ai->regs, RADEON_CUR2_CLR1, 0 ); 197 OUTREG( ai->regs, RADEON_CUR_HORZ_VERT_OFF, RADEON_CUR_LOCK 200 OUTREG( ai->regs, RADEON_CUR_HORZ_VERT_POSN, RADEON_CUR_LOCK 203 OUTREG( ai->regs, RADEON_CUR_OFFSET, 206 OUTREG( ai->regs, RADEON_CUR2_HORZ_VERT_OFF, RADEON_CUR2_LOCK 209 OUTREG( ai->regs, RADEON_CUR2_HORZ_VERT_POSN, RADEON_CUR2_LOCK 212 OUTREG( a [all...] |
H A D | overlay.c | 68 OUTREG( regs, RADEON_OV0_SCALE_CNTL, RADEON_SCALER_SOFT_RESET ); 69 OUTREG( regs, RADEON_OV0_AUTO_FLIP_CNTRL, si->overlay_mgr.auto_flip_reg ); 70 OUTREG( regs, RADEON_OV0_FILTER_CNTL, // use fixed filter coefficients 75 OUTREG( regs, RADEON_OV0_KEY_CNTL, RADEON_GRAPHIC_KEY_FN_EQ | 78 OUTREG( regs, RADEON_OV0_TEST, 0 ); 79 // OUTREG( regs, RADEON_FCP_CNTL, RADEON_FCP_CNTL_GND ); // disable capture clock 80 // OUTREG( regs, RADEON_CAP0_TRIG_CNTL, 0 ); // disable capturing 81 OUTREG( regs, RADEON_OV0_REG_LOAD_CNTL, 0 ); 83 OUTREG( regs, RADEON_OV0_DEINTERLACE_PATTERN, 89 OUTREG( reg [all...] |
H A D | flat_panel.c | 112 OUTREG( regs, RADEON_FP_HORZ_STRETCH, values->fp_horz_stretch ); 113 OUTREG( regs, RADEON_FP_VERT_STRETCH, values->fp_vert_stretch ); 266 OUTREG( regs, RADEON_FP_H2_SYNC_STRT_WID, values->fp2_h_sync_strt_wid ); 267 OUTREG( regs, RADEON_FP_V2_SYNC_STRT_WID, values->fp2_v_sync_strt_wid ); 270 OUTREG( regs, RADEON_FP_H_SYNC_STRT_WID, values->fp_h_sync_strt_wid ); 271 OUTREG( regs, RADEON_FP_V_SYNC_STRT_WID, values->fp_v_sync_strt_wid ); 277 OUTREG( regs, RADEON_GRPH_BUFFER_CNTL, 282 OUTREG( regs, RADEON_BIOS_4_SCRATCH, values->bios_4_scratch); 283 OUTREG( regs, RADEON_BIOS_5_SCRATCH, values->bios_5_scratch); 284 OUTREG( reg [all...] |
H A D | monitor_detection.c | 65 OUTREG(regs, info->port, value); 112 OUTREG(regs, RADEON_CRTC_EXT_CNTL, value); 121 OUTREG(regs, RADEON_DAC_EXT_CNTL, value); 128 OUTREG(regs, RADEON_DAC_CNTL, value); 143 OUTREG(regs, RADEON_DAC_CNTL, old_dac_cntl); 144 OUTREG(regs, RADEON_DAC_EXT_CNTL, old_dac_ext_cntl); 145 OUTREG(regs, RADEON_CRTC_EXT_CNTL, old_crtc_ext_cntl); 189 OUTREG(regs, RADEON_CRTC2_GEN_CNTL, value); 196 OUTREG(regs, RADEON_TV_DAC_CNTL, value); 202 OUTREG(reg [all...] |
H A D | internal_tv_out.c | 99 OUTREG( regs, mapping->address, *(uint32 *)((char *)(values) + mapping->offset) ); 135 OUTREG( regs, RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_TV_HOST_RD_WT_CNTL_RD); 148 OUTREG( regs, RADEON_TV_HOST_RD_WT_CNTL, 0); 168 OUTREG( regs, RADEON_TV_HOST_WRITE_DATA, value ); 169 OUTREG( regs, RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_TV_HOST_RD_WT_CNTL_WT ); 182 OUTREG( regs, RADEON_TV_HOST_RD_WT_CNTL, 0 ); 210 OUTREG( ai->regs, RADEON_TV_MASTER_CNTL,
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H A D | EngineManagment.c | 86 OUTREG( ai->regs, RADEON_RB2D_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); 87 OUTREG( ai->regs, RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN |
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H A D | monitor_routing.c | 424 OUTREG( regs, RADEON_DAC_CNTL, values->dac_cntl ); 425 OUTREG( regs, RADEON_DAC_CNTL2, values->dac_cntl2 ); 428 OUTREG( regs, RADEON_DISP_OUTPUT_CNTL, values->disp_output_cntl ); 438 OUTREG( regs, RADEON_DISP_HW_DEBUG, values->disp_hw_debug ); 442 OUTREG( regs, RADEON_DISP_TV_OUT_CNTL, values->disp_tv_out_cntl ); 462 OUTREG( regs, RADEON_TV_DAC_CNTL, values->tv_dac_cntl ); 466 OUTREG( regs, RADEON_TV_MASTER_CNTL, values->tv_master_cntl );
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/haiku/src/add-ons/kernel/drivers/graphics/radeon/ |
H A D | vip.c | 36 OUTREG( regs, RADEON_VIPH_REG_ADDR, (channel << 14) | address | 0x2000 ); 113 OUTREG( regs, RADEON_VIPH_REG_ADDR, (channel << 14) | address | 0x3000); 126 OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT, 144 OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT, (tmp & 0xffffff00) | RADEON_VIPH_TIMEOUT_STAT_VIPH_REGR_DIS); 165 OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT, 195 OUTREG( regs, RADEON_VIPH_REG_ADDR, (channel << 14) | (address & ~0x2000) ); 202 OUTREG( regs, RADEON_VIPH_REG_DATA, data ); 239 OUTREG( regs, RADEON_VIPH_REG_ADDR, 257 OUTREG( regs, RADEON_VIPH_REG_DATA, *(uint32*)(buffer + i)); 309 OUTREG( reg [all...] |
H A D | mem_controller.c | 163 OUTREG( regs, RADEON_AIC_PT_BASE, di->pci_gart.GATT.phys ); 167 OUTREG( regs, RADEON_AIC_LO_ADDR, si->memory[mt_PCI].virtual_addr_start ); 168 OUTREG( regs, RADEON_AIC_HI_ADDR, si->memory[mt_PCI].virtual_addr_start + 172 OUTREG( regs, RADEON_MC_AGP_LOCATION, 0xffffffc0 /* EK magic numbers from X.org 177 OUTREG( regs, RADEON_AGP_COMMAND, 0 ); 182 OUTREG( regs, RADEON_MC_FB_LOCATION, 188 OUTREG( regs, RADEON_DISPLAY_BASE_ADDRESS, si->memory[mt_local].virtual_addr_start ); 189 OUTREG( regs, RADEON_CRTC2_DISPLAY_BASE_ADDRESS, si->memory[mt_local].virtual_addr_start ); 190 OUTREG( regs, RADEON_OV0_BASE_ADDRESS, si->memory[mt_local].virtual_addr_start );
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H A D | pll_access.c | 52 OUTREG( regs, RADEON_CLOCK_CNTL_INDEX, tmp ); 54 OUTREG( regs, RADEON_CLOCK_CNTL_INDEX, save ); 78 OUTREG( regs, RADEON_CLOCK_CNTL_DATA, val );
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H A D | CP_setup.c | 234 OUTREG( regs, RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | 243 OUTREG( regs, RADEON_RBBM_SOFT_RESET, rbbm_soft_reset & 253 OUTREG( regs, RADEON_HOST_PATH_CNTL, host_path_cntl | RADEON_HDP_SOFT_RESET ); 255 OUTREG( regs, RADEON_HOST_PATH_CNTL, host_path_cntl ); 258 OUTREG( regs, RADEON_CLOCK_CNTL_INDEX, clock_cntl_index ); 260 OUTREG( regs, RADEON_RBBM_SOFT_RESET, rbbm_soft_reset); 266 OUTREG( regs, RADEON_CP_RB_WPTR, cur_read_ptr ); 312 OUTREG( di->regs, RADEON_CP_ME_RAM_ADDR, 0 ); 315 OUTREG( di->regs, RADEON_CP_ME_RAM_DATAH, microcode[i][1] ); 316 OUTREG( d [all...] |
H A D | DMA.c | 41 OUTREG( di->regs, RADEON_GEN_INT_STATUS, RADEON_VIDDMA_AK ); 170 OUTREG( di->regs, RADEON_DMA_VID_TABLE_ADDR, di->si->memory[mt_local].virtual_addr_start +
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