accelerants/radeon/overlay.c

68 	OUTREG( regs, RADEON_OV0_SCALE_CNTL, RADEON_SCALER_SOFT_RESET );
69 	OUTREG( regs, RADEON_OV0_AUTO_FLIP_CNTRL, si->overlay_mgr.auto_flip_reg );
70 	OUTREG( regs, RADEON_OV0_FILTER_CNTL, 			// use fixed filter coefficients
75 	OUTREG( regs, RADEON_OV0_KEY_CNTL, RADEON_GRAPHIC_KEY_FN_EQ |
78 	OUTREG( regs, RADEON_OV0_TEST, 0 );
79 //	OUTREG( regs, RADEON_FCP_CNTL, RADEON_FCP_CNTL_GND );	// disable capture clock
80 //	OUTREG( regs, RADEON_CAP0_TRIG_CNTL, 0 );				// disable capturing
81 	OUTREG( regs, RADEON_OV0_REG_LOAD_CNTL, 0 );
83 	OUTREG( regs, RADEON_OV0_DEINTERLACE_PATTERN,
89 			OUTREG( regs, std_gamma[i].reg,
263 	OUTREG( regs, RADEON_OV0_LIN_TRANS_A, dwOvRCb | dwOvRY );
264 	OUTREG( regs, RADEON_OV0_LIN_TRANS_B, dwOvROff | dwOvRCr );
265 	OUTREG( regs, RADEON_OV0_LIN_TRANS_C, dwOvGCb | dwOvGY );
266 	OUTREG( regs, RADEON_OV0_LIN_TRANS_D, dwOvGOff | dwOvGCr );
267 	OUTREG( regs, RADEON_OV0_LIN_TRANS_E, dwOvBCb | dwOvBY );
268 	OUTREG( regs, RADEON_OV0_LIN_TRANS_F, dwOvBOff | dwOvBCr );
336 	OUTREG( regs, RADEON_OV0_GRAPHICS_KEY_CLR_LOW, min32 );
337 	OUTREG( regs, RADEON_OV0_GRAPHICS_KEY_CLR_HIGH, max32 );
338 	OUTREG( regs, RADEON_OV0_KEY_CNTL,
849 	OUTREG( regs, RADEON_OV0_REG_LOAD_CNTL, RADEON_REG_LD_CTL_LOCK );
856 	OUTREG( regs, RADEON_OV0_VID_BUF0_BASE_ADRS, offset );
857 	OUTREG( regs, RADEON_OV0_VID_BUF_PITCH0_VALUE, node->buffer.bytes_per_row );
858 	OUTREG( regs, RADEON_OV0_H_INC, p1_h_inc | (p23_h_inc << 16) );
859 	OUTREG( regs, RADEON_OV0_STEP_BY, factors->p1_step_by | (factors->p23_step_by << 8) );
860 	OUTREG( regs, RADEON_OV0_V_INC, v_inc );
862 	OUTREG( regs,
865 	OUTREG( regs,
869 	OUTREG( regs, RADEON_OV0_P1_BLANK_LINES_AT_TOP,
871 	OUTREG( regs, RADEON_OV0_P1_X_START_END, p1_x_end | (p1_x_start << 16) );
872 	OUTREG( regs, RADEON_OV0_P1_H_ACCUM_INIT, p1_h_accum_init );
873 	OUTREG( regs, RADEON_OV0_P1_V_ACCUM_INIT, p1_v_accum_init );
875 	OUTREG( regs, RADEON_OV0_P23_BLANK_LINES_AT_TOP,
877 	OUTREG( regs, RADEON_OV0_P2_X_START_END,
879 	OUTREG( regs, RADEON_OV0_P3_X_START_END,
881 	OUTREG( regs, RADEON_OV0_P23_H_ACCUM_INIT, p23_h_accum_init );
882 	OUTREG( regs, RADEON_OV0_P23_V_ACCUM_INIT, p23_v_accum_init );
884 	OUTREG( regs, RADEON_OV0_TEST, node->test_reg );
897 			OUTREG( regs, RADEON_OV0_SCALE_CNTL, scale_ctrl |
902 			OUTREG( regs, RADEON_OV0_SCALE_CNTL, scale_ctrl);
906 			OUTREG( regs, RADEON_OV0_SCALE_CNTL, scale_ctrl |
913 	OUTREG( regs, RADEON_OV0_AUTO_FLIP_CNTRL,
916 	OUTREG( regs, RADEON_OV0_REG_LOAD_CNTL, 0 );
936 	OUTREG( ai->regs, RADEON_OV0_SCALE_CNTL, 0 );
978 /*	OUTREG( regs, RADEON_OV0_REG_LOAD_CNTL, RADEON_REG_LD_CTL_LOCK );
986 	/*OUTREG( regs,
989 	OUTREG( regs,
996 	OUTREG( regs, RADEON_OV0_AUTO_FLIP_CNTRL, si->overlay_mgr.auto_flip_reg );
999 //	OUTREG( regs, RADEON_OV0_REG_LOAD_CNTL, 0 );
1022 		OUTREG( ai->regs, RADEON_OV0_VID_BUF0_BASE_ADRS, offset);
1025 		OUTREG( ai->regs, RADEON_OV0_AUTO_FLIP_CNTRL, si->overlay_mgr.auto_flip_reg );