Searched refs:NV_VIO_SR_CLOCK_INDEX (Results 1 - 5 of 5) sorted by relevance

/linux-master/drivers/gpu/drm/nouveau/dispnv04/
H A Dhw.h245 uint8_t seq1 = NVReadVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX);
249 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20);
252 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20); /* reenable display */
H A Ddac.c157 saved_seq1 = NVReadVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX);
158 NVWriteVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX, saved_seq1 & ~0x20);
224 NVWriteVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX, saved_seq1);
H A Dhw.c117 seq1 = NVReadVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX);
121 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20);
123 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20);
H A Dnvreg.h133 # define NV_VIO_SR_CLOCK_INDEX 0x01 macro
H A Dcrtc.c226 seq1 |= (NVReadVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX) & ~0x20);
227 NVWriteVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX, seq1);
335 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x29;
337 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x21;

Completed in 112 milliseconds