Searched refs:NV_VIO_SR_CLOCK_INDEX (Results 1 - 5 of 5) sorted by relevance
/linux-master/drivers/gpu/drm/nouveau/dispnv04/ |
H A D | hw.h | 245 uint8_t seq1 = NVReadVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX); 249 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20); 252 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20); /* reenable display */
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H A D | dac.c | 157 saved_seq1 = NVReadVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX); 158 NVWriteVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX, saved_seq1 & ~0x20); 224 NVWriteVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX, saved_seq1);
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H A D | hw.c | 117 seq1 = NVReadVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX); 121 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20); 123 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20);
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H A D | nvreg.h | 133 # define NV_VIO_SR_CLOCK_INDEX 0x01 macro
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H A D | crtc.c | 226 seq1 |= (NVReadVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX) & ~0x20); 227 NVWriteVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX, seq1); 335 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x29; 337 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x21;
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