Searched refs:MI_BATCH_BUFFER_START (Results 1 - 10 of 10) sorted by relevance

/linux-master/drivers/gpu/drm/i915/selftests/
H A Digt_spinner.c186 *batch++ = MI_BATCH_BUFFER_START | BIT(8) | 1;
188 *batch++ = MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW;
190 *batch++ = MI_BATCH_BUFFER_START;
192 *batch++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
H A Di915_request.c1147 *cmd++ = MI_BATCH_BUFFER_START | 1 << 8 | 1;
1151 *cmd++ = MI_BATCH_BUFFER_START | 1 << 8;
1154 *cmd++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
/linux-master/drivers/gpu/drm/xe/instructions/
H A Dxe_mi_commands.h62 #define MI_BATCH_BUFFER_START __MI_INSTR(0x31) macro
/linux-master/drivers/gpu/drm/i915/gt/
H A Dgen2_engine_cs.c244 *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
264 *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
286 *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT | security;
H A Dintel_gpu_commands.h186 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) macro
468 *cs++ = MI_BATCH_BUFFER_START | flags;
H A Dselftest_hangcheck.c183 *batch++ = MI_BATCH_BUFFER_START | 1 << 8 | 1;
197 *batch++ = MI_BATCH_BUFFER_START | 1 << 8;
210 *batch++ = MI_BATCH_BUFFER_START | 2 << 6;
222 *batch++ = MI_BATCH_BUFFER_START | 2 << 6;
H A Dselftest_tlb.c118 *cs++ = MI_BATCH_BUFFER_START | BIT(8) | 1;
/linux-master/drivers/gpu/drm/xe/
H A Dxe_ring_ops.c96 dw[i++] = MI_BATCH_BUFFER_START | ppgtt_flag | XE_INSTR_NUM_DW(3);
/linux-master/drivers/gpu/drm/i915/
H A Di915_cmd_parser.c245 * MI_BATCH_BUFFER_START requires some special handling. It's not
249 CMD( MI_BATCH_BUFFER_START, SMI, !F, 0xFF, S ),
1515 if (cmd_desc_is(desc, MI_BATCH_BUFFER_START)) {
H A Di915_perf.c2070 MI_BATCH_BUFFER_START :
2113 MI_BATCH_BUFFER_START :
2206 config_length += 3; /* MI_BATCH_BUFFER_START */
2239 MI_BATCH_BUFFER_START :

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