/linux-master/arch/mips/alchemy/common/ |
H A D | irq.c | 917 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 2, au1000_ic0r0_dispatch); 918 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 3, au1000_ic0r1_dispatch); 919 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 4, au1000_ic1r0_dispatch); 920 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 5, au1000_ic1r1_dispatch); 957 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 2, alchemy_gpic_dispatch); 958 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 3, alchemy_gpic_dispatch); 959 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 4, alchemy_gpic_dispatch); 960 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 5, alchemy_gpic_dispatch); 995 do_IRQ(MIPS_CPU_IRQ_BASE + __ffs(r & 0xff));
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/linux-master/arch/mips/ath25/ |
H A D | ar2315_regs.h | 20 #define AR2315_IRQ_MISC (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */ 21 #define AR2315_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */ 22 #define AR2315_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */ 23 #define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */ 24 #define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */
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H A D | ar5312_regs.h | 17 #define AR5312_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */ 18 #define AR5312_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */ 19 #define AR5312_IRQ_ENET1 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */ 20 #define AR5312_IRQ_WLAN1 (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */ 21 #define AR5312_IRQ_MISC (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */
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H A D | devices.h | 9 #define ATH25_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE + 7) /* C0_CAUSE: 0x8000 */
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/linux-master/arch/mips/generic/ |
H A D | irq.c | 26 mips_cpu_fdc_irq = MIPS_CPU_IRQ_BASE + cp0_fdc_irq; 42 mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; 58 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
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/linux-master/arch/mips/include/asm/dec/ |
H A D | interrupts.h | 91 #define DEC_CPU_IRQ_BASE MIPS_CPU_IRQ_BASE /* first IRQ assigned to CPU */
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/linux-master/arch/mips/include/asm/ip32/ |
H A D | ip32_ints.h | 25 CRIME_IRQ_BASE = MIPS_CPU_IRQ_BASE + 8,
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/linux-master/arch/mips/include/asm/ |
H A D | jazz.h | 206 #define JAZZ_TIMER_IRQ (MIPS_CPU_IRQ_BASE+6)
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/linux-master/arch/mips/include/asm/mach-bcm63xx/ |
H A D | irq.h | 6 #define MIPS_CPU_IRQ_BASE 0 macro
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/linux-master/arch/mips/include/asm/mach-cavium-octeon/ |
H A D | irq.h | 12 #define MIPS_CPU_IRQ_BASE OCTEON_IRQ_SW0 macro
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/linux-master/arch/mips/include/asm/mach-cobalt/ |
H A D | irq.h | 40 #define MIPS_CPU_IRQ_BASE 16 macro 42 #define GT641XX_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 2) 43 #define RAQ2_SCSI_IRQ (MIPS_CPU_IRQ_BASE + 3) 44 #define ETH0_IRQ (MIPS_CPU_IRQ_BASE + 3) 45 #define QUBE1_ETH0_IRQ (MIPS_CPU_IRQ_BASE + 4) 46 #define ETH1_IRQ (MIPS_CPU_IRQ_BASE + 4) 47 #define SERIAL_IRQ (MIPS_CPU_IRQ_BASE + 5) 48 #define SCSI_IRQ (MIPS_CPU_IRQ_BASE + 5) 49 #define I8259_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 6)
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/linux-master/arch/mips/include/asm/mach-db1x00/ |
H A D | irq.h | 16 #ifndef MIPS_CPU_IRQ_BASE 17 #define MIPS_CPU_IRQ_BASE 0 macro
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/linux-master/arch/mips/include/asm/mach-loongson32/ |
H A D | irq.h | 14 #define MIPS_CPU_IRQ_BASE 0 macro 15 #define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x)) 26 #define MIPS_CPU_IRQS (MIPS_CPU_IRQ(7) + 1 - MIPS_CPU_IRQ_BASE)
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/linux-master/arch/mips/include/asm/sgi/ |
H A D | ip22.h | 28 #define SGINT_CPU MIPS_CPU_IRQ_BASE /* MIPS CPU define 8 interrupt sources */
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/linux-master/arch/mips/sni/ |
H A D | pcimt.c | 281 do_IRQ(MIPS_CPU_IRQ_BASE + 7); 283 do_IRQ(MIPS_CPU_IRQ_BASE + 6);
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/linux-master/arch/mips/txx9/generic/ |
H A D | irq_tx4927.c | 38 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + TX4927_IRC_INT,
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H A D | irq_tx4938.c | 26 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + TX4938_IRC_INT,
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/linux-master/arch/mips/txx9/rbtx4927/ |
H A D | irq.c | 47 * MIPS_CPU_IRQ_BASE+00 Software 0 48 * MIPS_CPU_IRQ_BASE+01 Software 1 49 * MIPS_CPU_IRQ_BASE+02 Cascade TX4927-CP0 50 * MIPS_CPU_IRQ_BASE+03 Multiplexed -- do not use 51 * MIPS_CPU_IRQ_BASE+04 Multiplexed -- do not use 52 * MIPS_CPU_IRQ_BASE+05 Multiplexed -- do not use 53 * MIPS_CPU_IRQ_BASE+06 Multiplexed -- do not use 54 * MIPS_CPU_IRQ_BASE+07 CPU TIMER 177 irq = MIPS_CPU_IRQ_BASE + 7; 183 irq = MIPS_CPU_IRQ_BASE [all...] |
/linux-master/drivers/irqchip/ |
H A D | irq-ath79-cpu.c | 51 do_IRQ(MIPS_CPU_IRQ_BASE + irq);
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/linux-master/arch/mips/bcm63xx/ |
H A D | irq.c | 528 irq = MIPS_CPU_IRQ_BASE + i; 537 irq = MIPS_CPU_IRQ_BASE + 2; 542 irq = MIPS_CPU_IRQ_BASE + 3;
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/linux-master/arch/mips/cavium-octeon/ |
H A D | octeon-irq.c | 2980 do_IRQ(fls(cop0_cause) - 9 + MIPS_CPU_IRQ_BASE);
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/linux-master/arch/mips/cobalt/ |
H A D | irq.c | 37 do_IRQ(MIPS_CPU_IRQ_BASE + 3); 39 do_IRQ(MIPS_CPU_IRQ_BASE + 4); 41 do_IRQ(MIPS_CPU_IRQ_BASE + 5); 43 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
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/linux-master/arch/mips/include/asm/mach-ath79/ |
H A D | irq.h | 9 #define MIPS_CPU_IRQ_BASE 0 macro 12 #define ATH79_CPU_IRQ(_x) (MIPS_CPU_IRQ_BASE + (_x))
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/linux-master/arch/mips/include/asm/mach-au1x00/ |
H A D | au1000.h | 39 #define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8) 46 #define ALCHEMY_GPIC_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
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/linux-master/arch/mips/include/asm/mach-generic/ |
H A D | irq.h | 23 #ifndef MIPS_CPU_IRQ_BASE 25 #define MIPS_CPU_IRQ_BASE 16 macro 27 #define MIPS_CPU_IRQ_BASE 0 macro
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