Searched refs:MIPSInst_RS (Results 1 - 3 of 3) sorted by relevance

/linux-master/arch/mips/kernel/
H A Dmips-r2-to-r6-emul.c84 (s32)regs->regs[MIPSInst_RS(ir)] +
93 (s64)regs->regs[MIPSInst_RS(ir)] +
107 regs->regs[MIPSInst_RS(ir)] |
111 if (MIPSInst_RS(ir))
120 if (MIPSInst_RS(ir))
134 (s32)((u32)regs->regs[MIPSInst_RS(ir)] +
143 (s32)((u32)regs->regs[MIPSInst_RS(ir)] -
147 if (IS_ENABLED(CONFIG_32BIT) || MIPSInst_RS(ir))
156 if (IS_ENABLED(CONFIG_32BIT) || MIPSInst_RS(ir))
170 (u64)regs->regs[MIPSInst_RS(i
[all...]
/linux-master/arch/mips/include/asm/
H A Dinst.h29 #define MIPSInst_RS(x) ((MIPSInst(x) & 0x03e00000) >> I_RS_SFT) macro
/linux-master/arch/mips/math-emu/
H A Dcp1emu.c1050 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1068 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1085 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1102 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1119 switch (MIPSInst_RS(ir)) {
1193 switch (MIPSInst_RS(ir)) {
1349 if (!(MIPSInst_RS(ir) & 0x10))
1377 xcp->regs[MIPSInst_RS(ir)];

Completed in 109 milliseconds