Searched refs:MFC_STATE1_MASTER_RUN_CONTROL_MASK (Results 1 - 6 of 6) sorted by relevance

/linux-master/arch/powerpc/platforms/cell/spufs/
H A Dhw_ops.c231 sr1 = spu_mfc_sr1_get(spu) | MFC_STATE1_MASTER_RUN_CONTROL_MASK;
242 sr1 = spu_mfc_sr1_get(spu) & ~MFC_STATE1_MASTER_RUN_CONTROL_MASK;
H A Dbacking_ops.c301 sr1 = csa->priv1.mfc_sr1_RW | MFC_STATE1_MASTER_RUN_CONTROL_MASK;
312 sr1 = csa->priv1.mfc_sr1_RW & ~MFC_STATE1_MASTER_RUN_CONTROL_MASK;
H A Dswitch.c496 spu_mfc_sr1_set(spu, (MFC_STATE1_MASTER_RUN_CONTROL_MASK |
1043 MFC_STATE1_MASTER_RUN_CONTROL_MASK);
1055 MFC_STATE1_MASTER_RUN_CONTROL_MASK);
1882 spu_mfc_sr1_set(spu, MFC_STATE1_MASTER_RUN_CONTROL_MASK);
2148 MFC_STATE1_MASTER_RUN_CONTROL_MASK |
/linux-master/arch/powerpc/include/asm/
H A Dspu.h450 #define MFC_STATE1_MASTER_RUN_CONTROL_MASK 0x20ull macro
/linux-master/arch/powerpc/platforms/cell/
H A Dspu_base.c700 tmp &= ~MFC_STATE1_MASTER_RUN_CONTROL_MASK;
/linux-master/arch/powerpc/xmon/
H A Dxmon.c4164 tmp &= ~MFC_STATE1_MASTER_RUN_CONTROL_MASK;

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