Searched refs:MDIO_MMD_VEND1 (Results 1 - 22 of 22) sorted by relevance

/linux-master/drivers/net/phy/
H A Dnxp-c45-tja11xx.c380 ts->tv_nsec = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1,
382 ts->tv_nsec |= phy_read_mmd(priv->phydev, MDIO_MMD_VEND1,
384 ts->tv_sec = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1,
386 ts->tv_sec |= phy_read_mmd(priv->phydev, MDIO_MMD_VEND1,
411 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_nsec_0,
413 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_nsec_1,
415 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_sec_0,
417 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_sec_1,
451 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1,
459 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1,
[all...]
H A Dmediatek-ge-soc.c34 /* Registers on MDIO_MMD_VEND1 */
339 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
342 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
351 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
353 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP) >>
362 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5,
383 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B,
385 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B,
387 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D,
389 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_
[all...]
H A Dmediatek-ge.c40 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x123, 0xffff);
43 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xa6, 0x300);
62 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0xc6, 0x300);
65 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404);
66 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404);
H A Dteranetics.c39 if (!phy_read_mmd(phydev, MDIO_MMD_VEND1, 93))
54 if (!phy_read_mmd(phydev, MDIO_MMD_VEND1, 93)) {
H A Dadin.c278 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
282 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_RGMII_CFG_REG);
314 return phy_write_mmd(phydev, MDIO_MMD_VEND1,
324 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
328 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_RMII_CFG_REG);
341 return phy_write_mmd(phydev, MDIO_MMD_VEND1,
441 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_FLD_EN_REG);
456 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
461 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
521 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_CLK_CFG_RE
[all...]
H A Dadin1100.c198 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1,
203 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, ADIN_CRSM_STAT, ret,
233 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ADIN_CRSM_SFT_RST, ADIN_CRSM_SFT_RST_EN);
237 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, ADIN_CRSM_STAT, ret,
H A Dmxl-gpy.c166 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_TEMP_STA);
232 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_ADDRLO,
240 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_CMD, cmd);
249 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
256 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_DATA);
358 phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
367 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL);
485 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
532 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
550 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTR
[all...]
H A Dbcm84881.c209 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, 0x4011);
H A Dphy_device.c808 if (i == MDIO_MMD_VEND1 || i == MDIO_MMD_VEND2) {
850 if (i == MDIO_MMD_VEND1 || i == MDIO_MMD_VEND2) {
H A Dnxp-c45-tja11xx-macsec.c1612 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_FUNC_ENABLES,
/linux-master/drivers/net/phy/aquantia/
H A Daquantia_firmware.c96 phy_write_mmd(phydev, MDIO_MMD_VEND1,
99 phy_write_mmd(phydev, MDIO_MMD_VEND1,
102 phy_write_mmd(phydev, MDIO_MMD_VEND1,
116 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE5,
118 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE6,
121 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE1,
138 up_crc = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE2);
262 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CONTROL2,
280 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_SC,
284 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CONTROL
[all...]
H A Daquantia_hwmon.c44 int temp = phy_read_mmd(phydev, MDIO_MMD_VEND1, reg);
65 return phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, (u16)temp);
70 int val = phy_read_mmd(phydev, MDIO_MMD_VEND1, reg);
H A Daquantia_main.c252 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK,
257 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK,
356 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, config_reg);
484 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
494 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID);
501 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1);
596 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9);
616 err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
643 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
655 err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL
[all...]
/linux-master/drivers/net/ethernet/chelsio/cxgb3/
H A Daq100x.c71 int err = t3_phy_reset(phy, MDIO_MMD_VEND1, 3000);
86 err = t3_mdio_write(phy, MDIO_MMD_VEND1, AQ_IMASK_GLOBAL, IMASK_GLOBAL);
92 return t3_mdio_write(phy, MDIO_MMD_VEND1, AQ_IMASK_GLOBAL, 0);
99 t3_mdio_read(phy, MDIO_MMD_VEND1, AQ_IFLAG_GLOBAL, &v);
110 err = t3_mdio_read(phy, MDIO_MMD_VEND1, AQ_IFLAG_GLOBAL, &cause);
292 err = t3_mdio_read(phy, MDIO_MMD_VEND1, MDIO_CTRL1, &v);
319 t3_mdio_read(phy, MDIO_MMD_VEND1, AQ_FW_VERSION, &v);
328 err = t3_mdio_read(phy, MDIO_MMD_VEND1, MDIO_CTRL1, &v);
332 err = t3_mdio_change_bits(phy, MDIO_MMD_VEND1, MDIO_CTRL1,
/linux-master/drivers/net/ethernet/aquantia/atlantic/macsec/
H A Dmacsec_api.c83 aq_mss_mdio_write(hw, MDIO_MMD_VEND1,
86 aq_mss_mdio_write(hw, MDIO_MMD_VEND1,
94 aq_mss_mdio_write(hw, MDIO_MMD_VEND1,
97 aq_mss_mdio_write(hw, MDIO_MMD_VEND1,
108 aq_mss_mdio_write(hw, MDIO_MMD_VEND1,
111 aq_mss_mdio_write(hw, MDIO_MMD_VEND1, MSS_INGRESS_LUT_CTL_REGISTER_ADDR,
137 ret = aq_mss_mdio_write(hw, MDIO_MMD_VEND1,
142 ret = aq_mss_mdio_write(hw, MDIO_MMD_VEND1,
151 ret = aq_mss_mdio_read(hw, MDIO_MMD_VEND1,
157 ret = aq_mss_mdio_read(hw, MDIO_MMD_VEND1,
[all...]
/linux-master/drivers/net/ethernet/aquantia/atlantic/
H A Daq_phy.c165 val = aq_phy_read_reg(aq_hw, MDIO_MMD_VEND1,
168 aq_phy_write_reg(aq_hw, MDIO_MMD_VEND1,
/linux-master/drivers/net/dsa/mv88e6xxx/
H A Dpcs-639x.c679 { MDIO_MMD_VEND1, 0x8093, 0xcb5a, 0xffff },
680 { MDIO_MMD_VEND1, 0x8171, 0x7088, 0xffff },
681 { MDIO_MMD_VEND1, 0x80c9, 0x311a, 0xffff },
682 { MDIO_MMD_VEND1, 0x80a2, 0x8000, 0xff7f },
683 { MDIO_MMD_VEND1, 0x80a9, 0x0000, 0xfff0 },
684 { MDIO_MMD_VEND1, 0x80a3, 0x0000, 0xf8ff },
735 return mdiodev_c45_write(&mpcs->mdio, MDIO_MMD_VEND1, 0x8000, 0x58);
/linux-master/drivers/net/ethernet/microchip/
H A Dlan743x_ethtool.c1234 { ETH_SR_VSMMD_DEV_ID1, MDIO_MMD_VEND1, 0x0002},
1235 { ETH_SR_VSMMD_DEV_ID2, MDIO_MMD_VEND1, 0x0003},
1236 { ETH_SR_VSMMD_PCS_ID1, MDIO_MMD_VEND1, 0x0004},
1237 { ETH_SR_VSMMD_PCS_ID2, MDIO_MMD_VEND1, 0x0005},
1238 { ETH_SR_VSMMD_STS, MDIO_MMD_VEND1, 0x0008},
1239 { ETH_SR_VSMMD_CTRL, MDIO_MMD_VEND1, 0x0009},
/linux-master/include/uapi/linux/
H A Dmdio.h27 #define MDIO_MMD_VEND1 30 /* Vendor specific 1 */ macro
158 #define MDIO_DEVS_VEND1 MDIO_DEVS_PRESENT(MDIO_MMD_VEND1)
/linux-master/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_x550.c2389 MDIO_MMD_VEND1,
2397 MDIO_MMD_VEND1,
2406 MDIO_MMD_VEND1,
2422 MDIO_MMD_VEND1,
2503 MDIO_MMD_VEND1,
2512 MDIO_MMD_VEND1,
2519 MDIO_MMD_VEND1,
2528 MDIO_MMD_VEND1,
2535 MDIO_MMD_VEND1,
2543 MDIO_MMD_VEND1,
[all...]
H A Dixgbe_phy.c1302 MDIO_MMD_VEND1,
2808 status = hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, &reg);
2820 status = hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, reg);
/linux-master/drivers/net/dsa/sja1105/
H A Dsja1105_mdio.c20 if (mmd != MDIO_MMD_VEND1 && mmd != MDIO_MMD_VEND2)
46 if (mmd != MDIO_MMD_VEND1 && mmd != MDIO_MMD_VEND2)

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