Searched refs:MDIO_MMD_AN (Results 1 - 25 of 38) sorted by relevance

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/linux-master/drivers/net/phy/
H A Dbcm84881.c113 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN,
129 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
133 bmsr = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_C22 + MII_BMSR);
146 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
155 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
159 bmsr = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_C22 + MII_BMSR);
185 val = phy_read_mmd(phydev, MDIO_MMD_AN,
H A Dphy-c45.c239 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L,
248 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M,
286 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE,
297 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
326 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
346 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, reg,
370 ret = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
404 val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
425 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
478 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STA
[all...]
H A Dadin1100.c84 ret = phy_read_mmd(phydev, MDIO_MMD_AN, ADIN_AN_PHY_INST_STATUS);
117 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, ADIN_FORCED_MODE, ADIN_FORCED_MODE_EN);
120 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_AN, ADIN_FORCED_MODE, ADIN_FORCED_MODE_EN);
126 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_H,
135 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_H,
H A Dteranetics.c62 reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
H A Dmediatek-ge.c27 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
H A Dmarvell-88q2xxx.c104 { MDIO_MMD_AN, MDIO_AN_T1_CTRL, 0x0 },
122 { MDIO_MMD_AN, 0x8032, 0x2020 },
123 { MDIO_MMD_AN, 0x8031, 0xa28 },
124 { MDIO_MMD_AN, 0x8031, 0xc28 },
158 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_MMD_AN_MV_STAT);
260 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_MMD_AN_MV_STAT);
277 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_MMD_AN_MV_STAT2);
H A Drealtek.c590 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
594 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) {
610 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
632 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
636 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) {
653 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
H A Dbcm-phy-lib.c377 val = phy_read_mmd(phydev, MDIO_MMD_AN, BRCM_CL45VEN_EEE_CONTROL);
386 phy_write_mmd(phydev, MDIO_MMD_AN, BRCM_CL45VEN_EEE_CONTROL, (u32)val);
389 val = phy_read_mmd(phydev, MDIO_MMD_AN, BCM_CL45VEN_EEE_ADV);
405 phy_write_mmd(phydev, MDIO_MMD_AN, BCM_CL45VEN_EEE_ADV, (u32)val);
512 { "phy_lpi_count", MDIO_MMD_AN, BRCM_CL45VEN_EEE_LPI_CNT, 0, 16 },
H A Dmarvell10g.c630 err = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MV_AN_21X0_SERDES_CTRL2,
636 err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_AN,
644 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MV_AN_21X0_SERDES_CTRL2,
955 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MV_AN_CTRL1000,
1042 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
1099 val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000);
/linux-master/drivers/vfio/platform/reset/
H A Dvfio_platform_amdxgbe.c85 value = xmdio_read(xpcs_regs->ioaddr, MDIO_MMD_AN, MDIO_CTRL1);
87 xmdio_write(xpcs_regs->ioaddr, MDIO_MMD_AN, MDIO_CTRL1, value);
90 xmdio_write(xpcs_regs->ioaddr, MDIO_MMD_AN, MDIO_AN_INTMASK, 0);
93 xmdio_write(xpcs_regs->ioaddr, MDIO_MMD_AN, MDIO_AN_INT, 0);
/linux-master/drivers/net/ethernet/chelsio/cxgb3/
H A Daq100x.c134 MDIO_MMD_AN, MDIO_CTRL1,
147 MDIO_MMD_AN, MDIO_CTRL1,
162 err = t3_mdio_change_bits(phy, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
173 err = t3_mdio_change_bits(phy, MDIO_MMD_AN, AQ_1G_CTRL,
188 err = t3_mdio_change_bits(phy, MDIO_MMD_AN, MDIO_AN_ADVERTISE,
223 err = t3_mdio_read(phy, MDIO_MMD_AN, AQ_ANEG_STAT, &v);
/linux-master/drivers/net/ethernet/amd/xgbe/
H A Dxgbe-mdio.c184 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0);
189 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0);
194 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, XGBE_AN_CL73_INT_MASK);
407 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1);
416 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg);
493 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
494 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
532 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 2, 0);
533 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 1, 0);
534 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XN
[all...]
H A Dxgbe-phy-v1.c243 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
244 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
267 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
268 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
291 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
292 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
/linux-master/drivers/net/phy/qcom/
H A Dqca808x.c107 phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1,
163 ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_CHIP_TYPE);
204 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN,
257 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
400 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
492 return phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
523 val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
553 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
619 return phy_modify_mmd(phydev, MDIO_MMD_AN,
H A Dqca807x.c232 return phy_modify_mmd(phydev, MDIO_MMD_AN, reg, mask,
264 val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
283 val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
325 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, mask);
374 val = phy_read_mmd(priv->phy, MDIO_MMD_AN, reg);
387 val = phy_read_mmd(priv->phy, MDIO_MMD_AN, reg);
392 phy_write_mmd(priv->phy, MDIO_MMD_AN, reg, val);
667 MDIO_MMD_AN,
780 control_dac = phy_read_mmd(phydev, MDIO_MMD_AN,
789 return phy_write_mmd(phydev, MDIO_MMD_AN,
[all...]
H A Dqcom-phy-lib.c626 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
635 val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
643 return phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
657 ret = phy_modify_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_LED_GLOBAL,
664 ret = phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
H A Dqca83xx.c113 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0);
/linux-master/drivers/net/ethernet/sfc/falcon/
H A Dmdio_10g.c55 if (mmd != MDIO_MMD_AN) {
285 ef4_mdio_write(efx, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg);
291 reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_CTRL1);
293 ef4_mdio_write(efx, MDIO_MMD_AN, MDIO_CTRL1, reg);
307 ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_LPA));
H A Dtenxpress.c263 reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_STAT1);
446 reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL);
449 reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
473 ef4_mdio_set_flag(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
/linux-master/drivers/net/phy/aquantia/
H A Daquantia_main.c222 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
242 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2);
247 err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2,
265 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2);
277 irq_status = phy_read_mmd(phydev, MDIO_MMD_AN,
297 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
317 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1);
422 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV);
446 return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
569 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT
[all...]
/linux-master/drivers/net/
H A Dmdio.c142 mdio_set_flag(mdio, mdio->prtad, MDIO_MMD_AN, MDIO_CTRL1,
153 reg = mdio->mdio_read(mdio->dev, mdio->prtad, MDIO_MMD_AN, addr);
259 reg = mdio->mdio_read(mdio->dev, mdio->prtad, MDIO_MMD_AN,
277 MDIO_MMD_AN, MDIO_STAT1);
430 reg = mdio->mdio_read(mdio->dev, mdio->prtad, MDIO_MMD_AN,
448 MDIO_MMD_AN, MDIO_STAT1);
574 devad = MDIO_MMD_AN;
/linux-master/drivers/net/pcs/
H A Dpcs-xpcs.c438 ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV3, adv);
451 ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV2, adv);
462 return xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV1, adv);
474 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_CTRL1);
480 return xpcs_write(xpcs, MDIO_MMD_AN, MDIO_CTRL1, ret);
490 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_AN_LPA);
521 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_AN_LPA + i);
962 an_stat1 = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_STAT1);
/linux-master/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_phy.c1108 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, &autoneg_reg);
1115 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, autoneg_reg);
1118 MDIO_MMD_AN, &autoneg_reg);
1142 MDIO_MMD_AN, autoneg_reg);
1145 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, &autoneg_reg);
1152 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, autoneg_reg);
1160 MDIO_MMD_AN, &autoneg_reg);
1165 MDIO_MMD_AN, autoneg_reg);
1340 MDIO_MMD_AN,
1348 MDIO_MMD_AN,
[all...]
H A Dixgbe_x550.c1981 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
2438 MDIO_MMD_AN, &reg);
2445 MDIO_MMD_AN, &reg);
2488 MDIO_MMD_AN, &reg);
2496 MDIO_MMD_AN, reg);
2663 ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
2668 ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
2715 MDIO_MMD_AN,
2879 MDIO_MMD_AN,
3115 MDIO_MMD_AN,
[all...]
/linux-master/include/uapi/linux/
H A Dmdio.h25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */ macro
156 #define MDIO_DEVS_AN MDIO_DEVS_PRESENT(MDIO_MMD_AN)

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