Searched refs:MDIO_CTRL1 (Results 1 - 25 of 26) sorted by relevance

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/linux-master/drivers/vfio/platform/reset/
H A Dvfio_platform_amdxgbe.c69 pcs_value = xmdio_read(xpcs_regs->ioaddr, MDIO_MMD_PCS, MDIO_CTRL1);
71 xmdio_write(xpcs_regs->ioaddr, MDIO_MMD_PCS, MDIO_CTRL1, pcs_value);
77 MDIO_CTRL1);
85 value = xmdio_read(xpcs_regs->ioaddr, MDIO_MMD_AN, MDIO_CTRL1);
87 xmdio_write(xpcs_regs->ioaddr, MDIO_MMD_AN, MDIO_CTRL1, value);
/linux-master/drivers/net/ethernet/chelsio/cxgb3/
H A Daq100x.c123 MDIO_MMD_PMAPMD, MDIO_CTRL1,
134 MDIO_MMD_AN, MDIO_CTRL1,
147 MDIO_MMD_AN, MDIO_CTRL1,
197 MDIO_MMD_PMAPMD, MDIO_CTRL1,
292 err = t3_mdio_read(phy, MDIO_MMD_VEND1, MDIO_CTRL1, &v);
328 err = t3_mdio_read(phy, MDIO_MMD_VEND1, MDIO_CTRL1, &v);
332 err = t3_mdio_change_bits(phy, MDIO_MMD_VEND1, MDIO_CTRL1,
H A Dael1002.c148 MDIO_MMD_PMAPMD, MDIO_CTRL1,
H A Dt3_hw.c358 err = t3_mdio_change_bits(phy, mmd, MDIO_CTRL1, MDIO_CTRL1_LPOWER,
364 err = t3_mdio_read(phy, mmd, MDIO_CTRL1, &ctl);
/linux-master/drivers/net/ethernet/sfc/falcon/
H A Dmdio_10g.c39 ef4_mdio_write(port, mmd, MDIO_CTRL1, MDIO_CTRL1_RESET);
43 ctrl = ef4_mdio_read(port, mmd, MDIO_CTRL1);
86 stat = ef4_mdio_read(efx, mmd, MDIO_CTRL1);
188 MDIO_CTRL1, MDIO_PMA_CTRL1_LOOPBACK,
191 MDIO_CTRL1, MDIO_PCS_CTRL1_LOOPBACK,
194 MDIO_CTRL1, MDIO_PHYXS_CTRL1_LOOPBACK,
207 ef4_mdio_set_flag(efx, mmd, MDIO_CTRL1,
291 reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_CTRL1);
293 ef4_mdio_write(efx, MDIO_MMD_AN, MDIO_CTRL1, reg);
H A Dqt202x_phy.c204 ef4_mdio_set_flag(efx, MDIO_MMD_PMAPMD, MDIO_CTRL1,
207 ef4_mdio_set_flag(efx, MDIO_MMD_PMAPMD, MDIO_CTRL1,
/linux-master/drivers/net/ethernet/amd/xgbe/
H A Dxgbe-phy-v1.c322 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
325 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
330 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
378 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
381 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
421 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
424 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
464 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
467 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
657 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
[all...]
H A Dxgbe-pci.c446 pdata->lpm_ctrl = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
448 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, pdata->lpm_ctrl);
462 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, pdata->lpm_ctrl);
H A Dxgbe-platform.c498 pdata->lpm_ctrl = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
500 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, pdata->lpm_ctrl);
516 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, pdata->lpm_ctrl);
H A Dxgbe-mdio.c368 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_CTRL1);
377 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_CTRL1, reg);
407 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1);
416 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg);
1556 dev_dbg(dev, "PCS Control Reg (%#06x) = %#06x\n", MDIO_CTRL1,
1557 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1));
1569 dev_dbg(dev, "Auto-Neg Control Reg (%#06x) = %#06x\n", MDIO_CTRL1,
1570 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1));
/linux-master/drivers/net/pcs/
H A Dpcs-xpcs-wx.c197 val = xpcs_read(xpcs, MDIO_MMD_PMAPMD, MDIO_CTRL1);
199 xpcs_write(xpcs, MDIO_MMD_PMAPMD, MDIO_CTRL1, val);
203 xpcs_write(xpcs, MDIO_MMD_PMAPMD, MDIO_CTRL1, 0);
204 xpcs_write(xpcs, MDIO_MMD_PCS, MDIO_CTRL1, 0);
H A Dpcs-xpcs.c271 ret = xpcs_read(xpcs, dev, MDIO_CTRL1);
298 ret = xpcs_write(xpcs, dev, MDIO_CTRL1, MDIO_CTRL1_RESET);
387 ret = xpcs_read_vpcs(xpcs, MDIO_CTRL1);
391 ret = xpcs_write_vpcs(xpcs, MDIO_CTRL1, ret | DW_USXGMII_EN);
395 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1);
402 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, ret);
406 ret = xpcs_read_vpcs(xpcs, MDIO_CTRL1);
410 ret = xpcs_write_vpcs(xpcs, MDIO_CTRL1, ret | DW_USXGMII_RST);
474 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_CTRL1);
480 return xpcs_write(xpcs, MDIO_MMD_AN, MDIO_CTRL1, re
[all...]
/linux-master/drivers/net/phy/
H A Dbcm84881.c27 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
146 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
H A Dphy-c45.c56 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
70 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
117 ctrl1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1);
167 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, ctrl1);
321 u16 reg = MDIO_CTRL1;
341 u16 reg = MDIO_CTRL1;
362 u16 reg = MDIO_CTRL1;
425 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
605 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1);
1235 return phy_modify_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1,
[all...]
H A Dmarvell-88q2xxx.c105 { MDIO_MMD_PMAPMD, MDIO_CTRL1,
109 { MDIO_MMD_PMAPMD, MDIO_CTRL1, 0x0 },
110 { MDIO_MMD_PCS, MDIO_CTRL1, 0x0 },
511 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
527 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
H A Dmarvell10g.c357 err = phy_modify_mmd(phydev, MDIO_MMD_PCS, unit + MDIO_CTRL1,
363 unit + MDIO_CTRL1, val,
H A Dbcm7xxx.c606 case MDIO_CTRL1:
H A Dadin.c206 { MDIO_MMD_PCS, MDIO_CTRL1, ADIN1300_CLOCK_STOP_REG },
H A Dphy.c1610 ret = phy_set_bits_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1,
/linux-master/drivers/net/
H A Dmdio.c142 mdio_set_flag(mdio, mdio->prtad, MDIO_MMD_AN, MDIO_CTRL1,
260 MDIO_CTRL1);
312 MDIO_CTRL1);
431 MDIO_CTRL1);
484 MDIO_CTRL1);
/linux-master/drivers/net/dsa/mv88e6xxx/
H A Dserdes.h47 #define MV88E6390_10G_CTRL1 (0x1000 + MDIO_CTRL1)
/linux-master/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_phy.c421 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
444 status = hw->phy.ops.read_reg(hw, MDIO_CTRL1,
1159 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
1164 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
1388 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
1393 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
1415 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
1418 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
1422 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
2808 status = hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND
[all...]
/linux-master/include/uapi/linux/
H A Dmdio.h31 #define MDIO_CTRL1 MII_BMCR macro
/linux-master/drivers/net/phy/aquantia/
H A Daquantia_main.c643 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
655 err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
/linux-master/drivers/net/dsa/sja1105/
H A Dsja1105_main.c2318 MDIO_MMD_VEND2, MDIO_CTRL1);

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