Searched refs:MC_SEQ_WR_CTL_D1_LP (Results 1 - 12 of 12) sorted by relevance

/linux-master/drivers/gpu/drm/radeon/
H A Dbtcd.h152 #define MC_SEQ_WR_CTL_D1_LP 0x2a80 macro
H A Dnid.h810 #define MC_SEQ_WR_CTL_D1_LP 0x2a80 macro
H A Dsid.h578 #define MC_SEQ_WR_CTL_D1_LP 0x2a80 macro
H A Dcikd.h703 #define MC_SEQ_WR_CTL_D1_LP 0x2a80 macro
H A Dbtc_dpm.c1852 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
2007 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
H A Devergreend.h328 #define MC_SEQ_WR_CTL_D1_LP 0x2a80 macro
H A Dcypress_dpm.c1002 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_WR_CTL_D1_LP >> 2;
H A Dni_dpm.c2798 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
2894 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
H A Dci_dpm.c4408 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
4606 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
H A Dsi_dpm.c5389 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
5489 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dsid.h579 #define MC_SEQ_WR_CTL_D1_LP 0xAA0 macro
/linux-master/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dsi_dpm.c5926 *out_reg = MC_SEQ_WR_CTL_D1_LP;
6026 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));

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