Searched refs:MC_SEQ_WR_CTL_D0_LP (Results 1 - 12 of 12) sorted by relevance

/linux-master/drivers/gpu/drm/radeon/
H A Dbtcd.h151 #define MC_SEQ_WR_CTL_D0_LP 0x2a7c macro
H A Dnid.h809 #define MC_SEQ_WR_CTL_D0_LP 0x2a7c macro
H A Dsid.h577 #define MC_SEQ_WR_CTL_D0_LP 0x2a7c macro
H A Dcikd.h702 #define MC_SEQ_WR_CTL_D0_LP 0x2a7c macro
H A Dbtc_dpm.c1849 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
2006 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
H A Devergreend.h327 #define MC_SEQ_WR_CTL_D0_LP 0x2a7c macro
H A Dcypress_dpm.c998 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_WR_CTL_D0_LP >> 2;
H A Dni_dpm.c2795 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
2893 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
H A Dci_dpm.c4405 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
4605 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
H A Dsi_dpm.c5386 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
5488 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dsid.h578 #define MC_SEQ_WR_CTL_D0_LP 0xA9F macro
/linux-master/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dsi_dpm.c5923 *out_reg = MC_SEQ_WR_CTL_D0_LP;
6025 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));

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