Searched refs:L1 (Results 1 - 25 of 42) sorted by relevance

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/linux-master/arch/arc/kernel/
H A Dentry-compact.S152 ; if L2 IRQ interrupted a L1 ISR, disable preemption
154 ; This is to avoid a potential L1-L2-L1 scenario
155 ; -L1 IRQ taken
156 ; -L2 interrupts L1 (before L1 ISR could run)
160 ; But both L1 and L2 re-enabled, so another L1 can be taken
161 ; while prev L1 is still unserviced
165 ; L2 interrupting L1 implie
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/linux-master/security/apparmor/include/
H A Dlabel.h163 #define next_comb(I, L1, L2) \
173 /* for each combination of P1 in L1, and P2 in L2 */
174 #define label_for_each_comb(I, L1, L2, P1, P2) \
176 ((P1) = (L1)->vec[(I).i]) && ((P2) = (L2)->vec[(I).j]); \
177 (I) = next_comb(I, L1, L2))
179 #define fn_for_each_comb(L1, L2, P1, P2, FN) \
183 label_for_each_comb(i, (L1), (L2), (P1), (P2)) { \
243 #define fn_for_each2_XXX(L1, L2, P, FN, ...) \
247 label_for_each ## __VA_ARGS__(i, (L1), (L2), (P)) { \
253 #define fn_for_each_in_merge(L1, L
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H A Dperms.h168 * TODO: optimize the walk, currently does subwalk of L2 for each P in L1
186 #define xcheck_ns_labels(L1, L2, FN, args...) \
189 fn_for_each((L1), __p1, FN(__p1, (L2), args)); \
193 #define xcheck_labels_profiles(L1, L2, FN, args...) \
194 xcheck_ns_labels((L1), (L2), xcheck_ns_profile_label, (FN), args)
196 #define xcheck_labels(L1, L2, P, FN1, FN2) \
197 xcheck(fn_for_each((L1), (P), (FN1)), fn_for_each((L2), (P), (FN2)))
/linux-master/arch/arm/mm/
H A Dproc-xsc3.S41 * The cache line size of the L1 I, L1 D and unified L2 cache.
46 * The size of the L1 D cache.
62 * This macro cleans and invalidates the entire L1 D cache.
68 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line
113 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
173 mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
196 mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line
197 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
224 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1
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/linux-master/arch/sparc/net/
H A Dbpf_jit_64.h21 #define L1 0x11 macro
/linux-master/arch/m68k/lib/
H A Ddivsi3.S95 jpl L1
102 L1: movel sp@(8), d0 /* d0 = dividend */ label
H A Dudivsi3.S144 L1: addl d0,d0 | shift reg pair (p,a) one bit left label
152 jcc L1
/linux-master/arch/powerpc/perf/
H A Dpower9-pmu.c30 * | | *- L1/L2/L3 cache_sel |
177 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1_FIN);
178 CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1);
179 CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_L1_PREF);
180 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
181 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
182 CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1);
183 CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_WRITE);
H A Dpower8-pmu.c46 * | | *- L1/L2/L3 cache_sel |
80 * else if cache_sel[1]: # L1 event
133 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1);
134 CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1);
136 CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_L1_PREF);
137 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
138 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
139 CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1);
140 CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_WRITE);
H A Dgeneric-compat-pmu.c32 /* Instruction ERAT/L1-TLB miss */
46 /* Data ERAT/L1-TLB miss/reload */
52 /* L1 Dcache reload from memory */
54 /* L1 Dcache store miss */
64 /* L1 Dcache load miss */
109 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1);
110 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
111 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
H A Dpower10-pmu.c29 * | | | *- L1/L2/L3 cache_sel | |*-radix_scope_qual
133 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1);
134 CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1);
135 CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_LD_PREFETCH_CACHE_LINE_MISS);
136 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
137 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
138 CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1);
139 CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_REQ);
H A Disa207-common.c223 ret = PH(LVL, L1) | LEVEL(L1) | P(SNOOP, HIT);
301 ret = PM(LVL, L1);
/linux-master/arch/hexagon/lib/
H A Dmemset.S159 if (r2==#0) jump:nt .L1
186 if (p1) jump .L1
197 if (p0.new) jump:nt .L1
208 if (p0.new) jump:nt .L1
284 .L1:
/linux-master/lib/
H A Dtest_dynamic_debug.c92 enum cat_level_names { L0 = 22, L1, L2, L3, L4, L5, L6, L7 }; enumerator in enum:cat_level_names
94 "L0", "L1", "L2", "L3", "L4", "L5", "L6", "L7");
133 prdbg(L1);
/linux-master/arch/alpha/boot/
H A Dmain.c53 * code has the L1 page table identity-map itself in the second PTE
54 * in the L1 page table. Thus the L1-page is virtually addressable
59 #define L1 ((unsigned long *) 0x200802000) macro
71 pcb_va->ptbr = L1[1] >> 32;
H A Dbootp.c59 * code has the L1 page table identity-map itself in the second PTE
60 * in the L1 page table. Thus the L1-page is virtually addressable
65 #define L1 ((unsigned long *) 0x200802000) macro
77 pcb_va->ptbr = L1[1] >> 32;
H A Dbootpz.c108 * code has the L1 page table identity-map itself in the second PTE
109 * in the L1 page table. Thus the L1-page is virtually addressable
113 #define L1 ((unsigned long *) 0x200802000) macro
125 pcb_va->ptbr = L1[1] >> 32;
/linux-master/arch/riscv/lib/
H A Dtishift.S10 beqz a2, .L1
21 .L1:
/linux-master/arch/m68k/fpsp040/
H A Dsetox.S104 | 3.1 R := X + N*L1, where L1 := single-precision(-log2/64).
105 | 3.2 R := R + N*L2, L2 := extended-precision(-log2/64 - L1).
106 | Notes: a) The way L1 and L2 are chosen ensures L1+L2 approximate
108 | b) N*L1 is exact because N is no longer than 22 bits and
109 | L1 is no longer than 24 bits.
110 | c) The calculation X+N*L1 is also exact due to cancellation.
111 | Thus, R is practically X+N(L1+L2) to full 64 bits.
241 | 3.1 R := X + N*L1, wher
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/linux-master/arch/arm/mach-omap2/
H A Dsram242x.S39 str r3, [r2] @ go to L1-freq operation
42 mov r9, #0x1 @ set up for L1 voltage call
101 orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
105 str r5, [r4] @ Force transition to L1
196 orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
200 str r8, [r10] @ Force transition to L1
H A Dsram243x.S39 str r3, [r2] @ go to L1-freq operation
42 mov r9, #0x1 @ set up for L1 voltage call
101 orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
105 str r5, [r4] @ Force transition to L1
196 orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
200 str r8, [r10] @ Force transition to L1
/linux-master/arch/x86/lib/
H A Dcsum-copy_64.S163 .L1: /* .Lshort rejoins the common path here */
207 jmp .L1
/linux-master/tools/perf/util/
H A Dparse-events.l171 lc_type (L1-dcache|l1-d|l1d|L1-data|L1-icache|l1-i|l1i|L1-instruction|LLC|L2|dTLB|d-tlb|Data-TLB|iTLB|i-tlb|Instruction-TLB|branch|branches|bpu|btb|bpc|node)
/linux-master/drivers/cpufreq/
H A Ds5pv210-cpufreq.c110 L0, L1, L2, L3, L4, enumerator in enum:perf_level
126 {0, L1, 800*1000},
149 [L1] = {
178 /* L1 : [800/200/100][166/83][133/66][200/200] */
/linux-master/arch/alpha/lib/
H A Dev6-memset.S17 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
161 wh64 ($4) # L1 : memory subsystem write hint
339 wh64 ($4) # L1 : memory subsystem write hint
527 wh64 ($4) # L1 : memory subsystem write hint

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