Searched refs:GPR_T0 (Results 1 - 4 of 4) sorted by relevance
| /linux-master/arch/mips/kernel/ |
| H A D | pm-cps.c | 200 UASM_i_LA(pp, GPR_T0, (long)CKSEG0);
204 uasm_i_addiu(pp, GPR_T1, GPR_T0, cache_size);
214 uasm_i_cache(pp, op, 0, GPR_T0);
215 uasm_i_addiu(pp, GPR_T0, GPR_T0, cache->linesz);
217 uasm_i_cache(pp, op, i * cache->linesz, GPR_T0);
223 uasm_i_addiu(pp, GPR_T0, GPR_T0, unroll_lines * cache->linesz);
226 uasm_il_bne(pp, pr, GPR_T0, GPR_T1, lbl);
276 uasm_i_addiu(pp, GPR_T0, GPR_ZER
[all...] |
| /linux-master/arch/mips/kvm/ |
| H A D | entry.c | 246 UASM_i_LW(&p, GPR_T0, offsetof(struct kvm_vcpu_arch, pc), GPR_K1);
247 UASM_i_MTC0(&p, GPR_T0, C0_EPC);
288 uasm_i_mfc0(&p, GPR_T0, C0_GUESTCTL1);
290 uasm_i_ext(&p, GPR_T1, GPR_T0, MIPS_GCTL1_ID_SHIFT,
292 uasm_i_ins(&p, GPR_T0, GPR_T1, MIPS_GCTL1_RID_SHIFT,
294 uasm_i_mtc0(&p, GPR_T0, C0_GUESTCTL1);
542 uasm_i_mfhi(&p, GPR_T0);
543 UASM_i_SW(&p, GPR_T0, offsetof(struct kvm_vcpu_arch, hi), GPR_K1);
545 uasm_i_mflo(&p, GPR_T0);
546 UASM_i_SW(&p, GPR_T0, offseto
[all...] |
| /linux-master/arch/mips/mm/ |
| H A D | page.c | 467 build_copy_load(&buf, GPR_T0, off);
475 build_copy_store(&buf, GPR_T0, off);
489 build_copy_load(&buf, GPR_T0, off);
497 build_copy_store(&buf, GPR_T0, off);
515 build_copy_load(&buf, GPR_T0, off);
520 build_copy_store(&buf, GPR_T0, off);
533 build_copy_load(&buf, GPR_T0, off);
538 build_copy_store(&buf, GPR_T0, off);
557 build_copy_load(&buf, GPR_T0, off);
561 build_copy_store(&buf, GPR_T0, of
[all...] |
| /linux-master/arch/mips/include/asm/ |
| H A D | regdef.h | 30 #define GPR_T0 8 /* caller saved */ macro
81 #define GPR_T0 12 /* caller saved */ macro
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