Searched refs:GEN8_RING_CS_GPR (Results 1 - 10 of 10) sorted by last modified time
| /linux-master/drivers/gpu/drm/i915/ |
| H A D | intel_gvt_mmio_table.c | 1246 MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40);
1247 MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40);
1248 MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40);
1249 MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40);
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| H A D | i915_perf.c | 1942 #define CS_GPR(x) GEN8_RING_CS_GPR(base, x)
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| H A D | i915_cmd_parser.c | 651 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 0),
652 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 1),
653 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 2),
654 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 3),
655 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 4),
656 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 5),
657 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 6),
658 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 7),
659 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 8),
660 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BAS
[all...] |
| /linux-master/drivers/gpu/drm/i915/gvt/ |
| H A D | handlers.c | 2782 MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
2784 MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,
2786 MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,
2788 MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,
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| /linux-master/drivers/gpu/drm/i915/gt/ |
| H A D | intel_lrc.c | 1261 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));
1269 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));
1275 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));
1289 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));
1305 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));
1313 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));
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| H A D | selftest_lrc.c | 354 i915_mmio_reg_offset(GEN8_RING_CS_GPR(engine->mmio_base, 0)),
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| H A D | selftest_rps.c | 68 #define CS_GPR(x) GEN8_RING_CS_GPR(engine->mmio_base, x)
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| H A D | intel_engine_regs.h | 238 #define GEN8_RING_CS_GPR(base, n) _MMIO((base) + 0x600 + (n) * 8) macro
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| H A D | selftest_timeline.c | 782 const u32 gpr = i915_mmio_reg_offset(GEN8_RING_CS_GPR(rq->engine->mmio_base, 0));
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| /linux-master/drivers/gpu/drm/i915/selftests/ |
| H A D | i915_perf.c | 307 gpr0 = i915_mmio_reg_offset(GEN8_RING_CS_GPR(stream->engine->mmio_base, 0));
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