Searched refs:G1 (Results 1 - 10 of 10) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.cpp57 // FIXME: G1 reserved for now for large imm generation by frame code.
58 Reserved.set(SP::G1);
60 // G1-G4 can be used in applications.
126 // reserving G1 all of the time.
131 // Insert G1+%lo(offset) into the user.
132 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1)
136 // Emit G1 = G1 + I6
137 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
[all...]
H A DSparcFrameLowering.cpp57 // Emit this the hard way. This clobbers G1 which we always know is
64 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
66 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
67 .addReg(SP::G1).addImm(LO10(NumBytes));
69 .addReg(SP::O6).addReg(SP::G1);
77 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
79 BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1)
80 .addReg(SP::G1).addImm(LOX10(NumBytes));
82 .addReg(SP::O6).addReg(SP::G1);
183 // This clobbers G1 whic
[all...]
H A DSparcISelLowering.cpp1028 .Case("g0", SP::G0).Case("g1", SP::G1).Case("g2", SP::G2).Case("g3", SP::G3)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64A57FPLoadBalancing.cpp454 llvm::sort(GV, [](const Chain *G1, const Chain *G2) {
455 if (G1->size() != G2->size())
456 return G1->size() > G2->size();
457 if (G1->requiresFixup() != G2->requiresFixup())
458 return G1->requiresFixup() > G2->requiresFixup();
460 assert((G1 == G2 || (G1->startsBefore(G2) ^ G2->startsBefore(G1))) &&
462 return G1->startsBefore(G2);
/freebsd-11-stable/contrib/groff/src/roff/grog/
H A Dgrog.pl58 elsif (/^\.G1$sp/) {
/freebsd-11-stable/contrib/gdb/gdb/
H A Dsparc-stub.c110 enum regnames {G0, G1, G2, G3, G4, G5, G6, G7, enumerator in enum:regnames
/freebsd-11-stable/contrib/binutils/opcodes/
H A Dmips-opc.c119 #define G1 (T3 \ macro
785 {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 },
787 {"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 },
791 {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 },
793 {"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 },
972 {"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 },
976 {"multu", "d,s,t", 0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 },
1232 {"sync", "", 0x0000000f, 0xffffffff, INSN_SYNC, 0, I2|G1 },
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Analysis/
H A DDependenceAnalysis.cpp1411 APInt G1 = BM.abs(); local
1414 APInt::sdivrem(G0, G1, Q, R);
1418 G0 = G1; G1 = R;
1419 APInt::sdivrem(G0, G1, Q, R);
1421 G = G1;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/Disassembler/
H A DSparcDisassembler.cpp61 SP::G0, SP::G1, SP::G2, SP::G3,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/
H A DSparcAsmParser.cpp129 Sparc::G0, Sparc::G1, Sparc::G2, Sparc::G3,

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